参数资料
| 型号： | SP526CF-L |
| 厂商： | Exar Corporation |
| 文件页数： | 9/24页 |
| 文件大小： | 0K |
| 描述： | IC TXRX WAN MULTI-MODE 44LQFP |
| 产品变化通告： | Product Discontinuation 21/Dec/2011 |
| 标准包装： | 160 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 4/4 |
| 规程： | 多协议 |
| 电源电压： | 5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LQFP |
| 供应商设备封装： | 44-LQFP（10x10） |
| 包装： | 托盘 |
17
Rev: C Date:2/1/06
SP526 Multi–Mode Serial Transceiver
Copyright 2006 Sipex Corporation
The third type of receiver is a differential which
supports RS-422/V.11 signals. This receiver
has a typical input impedance of 10K
and a
differential threshold of
±0.3V, which complies
with the RS-422/V.11 specifications. Since the
characteristics of the RS-422 (V.11) receivers
are actually subsets of RS-485, the RS-422/
V.11 receivers can accept RS-485 signals.
However, these receivers cannot support 32
transceivers on the signal bus due to the lower
input impedance as specified in the RS-485
specifications.
V.11 receivers are used in
RS-422, RS-449, EIA-530, EIA-530A and V.36
as Category I signals for receiving clock, data,
and some control line signals not covered
by Category II V.10 circuits. The differential
receivers can receive signals up to at least
10Mbps.
All four receivers include an enable line for
tri-state of the receiver output allowing
convenient half-duplex configurations. When
the enable lines are at a logic LOW ("0") active,
the receiver outputs are high impedance and will
be at approximately 10k
during tri-state.
All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs are
open. For single-ended RS-232 receivers, there
are internal 5k
pull-down resistors on the
inputs which produces a logic high ("1") at the
receiver outputs. The single-ended RS-423
receivers produce a logic LOW ("0") on the
output when the inputs are open. This is due to
a pull-up device connected to the input. The
differential receivers have the same internal
pull-up device on the non-inverting input which
produces a logic HIGH ("1") at the receiver output.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external capaci-
tors, but uses a four–phase voltage shifting
technique to attain symmetrical 10V power
supplies. There is a free–running oscillator that
controls the four phases of the voltage shifting.
A description of each phase follows.
Phase 1
— V
SS charge storage —During this phase of
the clock cycle, the positive side of capacitors
C
1 and C2 are initially charged to +5V. Cl
+ is
then switched to ground and the charge in C
1
– is
transferred to C
2
–. Since C
2
+ is connected to
+5V, the voltage potential across capacitor C
2 is
now 10V.
Phase 2
— V
SS transfer — Phase two of the clock
connects the negative terminal of C
2 to the VSS
storage capacitor and the positive terminal of C
2
to ground, and transfers the generated –l0V to
C
3. Simultaneously, the positive side of
capacitor C
1 is switched to +5V and the
negative side is connected to ground.
Phase 3
— V
DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
1 produces –5V in the negative
terminal of C
1, which is applied to the negative
side of capacitor C
2. Since C2
+ is at +5V, the
voltage potential across C
2 is l0V.
C1
+
-
-5V
VCC = +5V
+5V
C2
-5V
C4
C3
+
-
+
-
+
VDD Storage Capacitor
VSS Storage Capacitor
Figure 30. Charge Pump — Phase 1
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