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参数资料
| 型号： | SP674AA |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封装： | 0.600 INCH, CERDIP-28 |
| 文件页数： | 14/14页 |
| 文件大小： | 204K |
| 代理商： | SP674AA |
11
Table 1. SPx74A Control Input Truth Table
CE CS R/C 12/8 A
0
OPERATION
0
xxxx
None
x
1
x
None
0
x
0
Initiate 12–Bit Conversion
0
x
1
Initiate 8–Bit Conversion
1
0
x
0
Initiate 12–Bit Conversion
1
0
x
1
Initiate 8–Bit Conversion
10
x
0
Initiate 12–Bit Conversion
10
x
1
Initiate 8–Bit Conversion
1
0
1
x
Enable 12–Bit Output
1
0100
Enable 8 MSB's Only
1
0101
Enable 4 LSB's plus 4
Trailing Zeroes
of these inputs in controlling the converter’s
operation is shown in Table 1, and the internal
control logic is shown in a simplified schematic
in Figure 6.
Conversion Start
A conversion may be initiated by a logic transi-
tion on any of the three inputs: CE, CS R/C, as
shown in Table 1. The last of the three to reach
the correct state starts the conversion, so one,
two or all three may be dynamically controlled.
The nominal delay from each is the same and all
three may change state simultaneously. In order
to assure that a particular input controls the start
of conversion, the other two should be setup at
least 50ns earlier. Refer to the convert mode
timing specifications. The Convert Mode timing
diagram is shown in Figure 8.
The output signal STS is the status flag and goes
high only when a conversion is in progress.
While STS is high, the output buffers remain in
a high impedance state so that data can not be
read. Also, when STS is high, an additional Start
Convert will not reset the converter or reinitiate
a conversion. Note, if A
0 changes state after a
conversion begins, an additional Start Convert
command will latch the new state of A
0 and
possibly cause a wrong cycle length for that
conversion (8–versus 12–bits).
CONTROLLING THE SPx74A
The SPx74A can be operated by most micropro-
cessor systems due to the control input pins and
on–chip logic. It may also be operated in the
“stand–alone” mode and enabled by the R/C
input pin. Full microprocessor control consists
of selecting an 8– or 12–bit conversion cycle,
initiating the conversion, and reading the output
data when ready. The output read has the options
of choosing either 12–bits at once or 8–bits
followed by 4–bits in a left–justified format. All
five control inputs are TTL/CMOS compatible
and include 12/8, CS, A
0, R/C and CE. The use
log input to pin 13 for the 0V to 10V range or to
pin 14 for the 0V to 20V range.
Bipolar
The gain and offset errors listed in the specifica-
tions may be adjusted to zero using the potenti-
ometers R
1 and R2 (See Figure 5). If adjustment
is not needed, either or both pots may be replaced
by a 50
, 1% metal film resistor.
To calibrate, connect the analog input signal to
pin 13 for a
±5V range or to pin 14 for a ±10V
range. First apply a DC input voltage 1
2 LSB
above negative full scale which is –4.9988V for
the
±5V range or –9.9976V for the ±10V range.
Adjust the offset potentiometer R
1 for flicker
between output codes 0000 0000 0000 and 0000
0000 0001. Next, apply a DC input voltage 11
2
LSB below positive full scale which is +4.9963V
for the
±5 range or +9.9927V for the ±10V range.
Adjust the gain potentiometer R
2 for flicker
between codes 1111 1111 1110 and 1111 1111
1111.
Alternative
The 100
potentiometer R
2 provides gain adjust
for 10V and 20V ranges. In some applications, a
full scale of 10.24V (for and LSB of 2.5mV) or
20.48 (for an LSB of 5.0mV) is more convenient.
For these, replace R
2 by a 50, 1% metal film
resistor. Then to provide gain adjust for the 10.24
range, add a 200
potentiometer and a 95
fixed resistor, all in series with pin 13. For the
20.48V range, add a 500
potentiometer and a
200
fixed resistor in series with pin 14.
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