4-6
DSP56853/854/855/857/858 User’s Manual
MOTOROLA
Preliminary
SIM Register Map
4
4.4 SIM Register Map
The System Integration Module (SIM) contains three programmable 16-bit registers. The
address range from $1FFF08 to $1FFF0F is allocated to the SIM. The register is accessed
by each of the eight-memory mapped addresses, delineated in Tables 4-7. To avoid
unpredictable behavior, reserved registers must not be written. A read from an address
without an associated register returns unknown data.
Table 4-4. Register Inputs/Outputs
Name
Type
Clock Domain
Function
MODE_CBA
Input
—
From MODEC, B, A input pads, captured at reset in SIM control
register to indicate software boot mode
PRAM_DBL
Output
CLK_IPB
Redirect program RAM accesses to external memory IF
DRAM_DBL
Output
CLK_IPB
Redirect data RAM accesses to external memory IF
STOP_DBL
Output
CLK_IPB
Direct the core to disable the STOP instruction
WAIT_DBL
Output
CLK_IPB
Direct the core to disable the WAIT instruction
Table 4-5. Power Mode Control Inputs/Outputs
Name
Type
Clock Domain
Function
STOPMD
Output
CLK_SYS_CONT Indicates SIM is in Stop mode
WAITMD
Output
CLK_SYS_CONT Indicates SIM is in Wait mode
RUNMD
Output
CLK_SYS_CONT Indicates SIM is in Run mode
OSC_LOPWR
Output
CLK_SYS_CONT
Puts oscillator into low power mode configuration during Stop
mode
PLL_SHUTDOWN
Output
CLK_SYS_CONT
Shuts down PLL and puts it into bypass mode when entering
Stop mode
P5STOP
Input
CLK_SYS_CONT Input from Core indicating Stop instruction executed
P5WAIT
Input
CLK_SYS_CONT Input from Core indicating Wait instruction executed
INT_PEND
Input
CLK_SYS_CONT Input from INTC indicating interrupt is pending
JTDEBREQ
Input
CLK_SYS_CONT Input from Core indicating a JTAG debug mode request
DE
Input
CLK_SYS_CONT Input from DE input pad used to enter OnCE debug mode
OMR6_SD
Input
CLK_SYS_CONT From core OMR6 register to enable fast stop mode recovery
BSCAN_EBL
Input
—
From external TAP controller indicating boundary scan mode
Table 4-6. Derived Clock Inputs
Name
Type
Clock Domain
Function
CLK_SYS_CONT_IN
Input
CLK_SYS_CONT
Continuous clock fed by synthesized clock tree originating
at SIM output CLK_SYS_CONT