Functional Description
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
12-19
Preliminary
12
eliminating either the receive or transmit interrupts, driving both channels from the same
set of interrupts. If this decision is made, it is necessary to be aware of the specific timing
of the receive and transmit interrupts, because the interrupts are not generated at the same
exact point in the frame timing, shown in Figure 12-6. If it is desired to run off a single set
of interrupts, the TX interrupts should be used. If RX interrupts are used, there may be
timing problems with the transmit data because this interrupt occurs a half-bit time before
the transmit data is used by the hardware.
Figure 12-6. Synchronous Mode Interrupt Timing
12.5.4 Network Mode with Mask Registers Implemented
In order to reduce interrupt overhead, a number of enhancements have been made to the
ESSI module. The enhancements incorporate the mask registers (TSM and RSM).
transfers using the mask registers. These figures duplicate the frame structure of
Figure 12-5 to illustrate the reduced amount of interrupt processing required. The
numbered circles and arrows in the figures identify discussion notes contained in Table 12.5.4.1 Operation Using TSM Register
When the TSM register is included in the design interrupt overhead can be reduced. If all
bits of the TSM register are set, the ESSI transmitter will continue to operate as previously
described. The TSM register is used to disable the STD pin on specific time-slots. This is
accomplished by writing the TSM with 0 in the time-slot bit location. Disabling a time slot
in this manner causes the time slot to be ignored by the ESSI. This means no data is
transferred to the Transmit Shift Register (TXSR), therefore interrupts are not generated
SCK
SC2
STX Register
TDE Status Bit / Interrupt
RDR Status Bit / Interrupt
Valid
Indefinite transition depends on SW interrupt processing
Invalid
TX Interrupt
RX Interrupt
TX Interrupt
RX Interrupt