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参数资料
| 型号： | SPAK56F802TA60 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 60 MHz, OTHER DSP, PQFP32 |
| 封装： | 7 X 7 MM, 0.80 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-32 |
| 文件页数： | 11/39页 |
| 文件大小： | 573K |
| 代理商： | SPAK56F802TA60 |
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Clock Operation
MOTOROLA
56F802 Technical Data
19
Figure 8. Flash Mass Erase Cycle
3.5 Clock Operation
The 56F802 device clock is derived from an on-chip relaxation oscillator. The internal PLL generates a
master reference frequency that determines the speed at which chip operations occur.
The PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2) must be set to 0 for internal
oscillator use.
3.5.1
Use of On-Chip Relaxation Oscillator
The 56F802 internal relaxation oscillator provides the chip clock without the need for an external crystal or
ceramic resonator. The frequency output of this internal oscillator can be corrected by adjusting the 8-bit
IOSCTL (internal oscillator control) register. Each bit added or deleted changes the output frequency of the
oscillator allowing incremental adjustment until the desired frequency is achieved. Figures 9 and 10 show
the typical characteristics of the 56F802 relaxation oscillator with respect to temperature and trim value.
During factory production test, an oscillator calibration procedure is executed which determines an
optimum trim value for a given device (8MHz at 25oC). This optimum trim value is then stored at address
$103F in the Data Flash Information Block and recalled during a trim routine in the boot sequence (executed
after power-up and RESET). This trim routine automatically sets the oscillator frequency by programming
the IOSCTL register with the optimum trim value.
Due to the inherent frequency tolerances required for SCI communication, changing the factory-trimmed
oscillator frequency is not recommended. If modification of the Boot Flash contents are required, code must
be included which retrieves the optimum trim value (from address $103F in the Data Flash Information
Block) and writes it to the IOSCTL register. Note that the IFREN bit in the Data Flash control register must
be set in order to read the Data Flash Information Block.
XADR
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
MAS1
IFREN
XE
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