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| 型号： | SPC5200CVR400R2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 15/72页 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 400MHZ 272-PBGA |
| 标准包装： | 500 |
| 系列： | MPC52xx |
| 处理器类型： | 32-位 MPC52xx PowerPC |
| 速度： | 400MHz |
| 电压： | 1.5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 272-BBGA |
| 供应商设备封装： | 272-PBGA（27x27） |
| 包装： | 带卷 (TR) |
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MPC5200B Data Sheet, Rev. 4
22
Freescale Semiconductor
Figure 9. PCI CLK Waveform
NOTES:
1. In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending
upon whether the clock frequency is above 33 MHz.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform as shown in Figure 9.
3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
NOTES:
1. See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven signal transitions drive
to their Voh or Vol level within one Tcyc.
Table 22. PCI CLK Specifications
Sym
Description
66 MHz
33 MHz
Units
Notes
SpecID
Min
Max
Min
Max
tcyc
PCI CLK Cycle Time
15
30
—ns
(1),(3)
A6.1
thigh
PCI CLK High Time
6
—11
—ns
—A6.2
tlow
PCI CLK Low Time
6
—11
—ns
—A6.3
—
PCI CLK Slew Rate
1.5
4
1
4
V/ns
(2)
A6.4
—
PCI Clock Jitter
(peak to peak)
—200
—
200
ps
—
Table 23. PCI Timing Parameters
Sym
Description
66 MHz
33 MHz
Units
Notes
SpecID
Min
Max
Min
Max
tval
CLK to Signal Valid Delay —
bused signals
262
11
ns
(1),(2),(3)
A6.5
tval(ptp)
CLK to Signal Valid Delay —
point to point
262
12
ns
(1),(2),(3)
A6.6
ton
Float to Active Delay
2
—2
—ns
(1)
A6.7
toff
Active to Float Delay
14
28
ns
(1)
A6.8
tsu
Input Setup Time to CLK —
bused signals
3
—7
—ns
(3),(4)
A6.9
tsu(ptp) Input Setup Time to CLK — point
to point
5
—10,12
—ns
(3),(4)
A6.10
th
Input Hold Time from CLK
0
—0
—ns
(4)
A6.11
tcyc
PCI CLK
tlow
thigh
0.4 Vcc
0.4 Vcc, p-to-p
0.3 Vcc
0.5 Vcc
0.6 Vcc
0.2 Vcc
(minimum)
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