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| 型号： | SPC5200CVR400R2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 3/72页 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 400MHZ 272-PBGA |
| 标准包装： | 500 |
| 系列： | MPC52xx |
| 处理器类型： | 32-位 MPC52xx PowerPC |
| 速度： | 400MHz |
| 电压： | 1.5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 272-BBGA |
| 供应商设备封装： | 272-PBGA（27x27） |
| 包装： | 带卷 (TR) |
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MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
11
1.2.1
System Oscillator Electrical Characteristics
1.2.2
RTC Oscillator Electrical Characteristics
1.2.3
System PLL Electrical Characteristics
1.2.4
e300 Core PLL Electrical Characteristics
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled
core PLL.
Table 8. System Oscillator Electrical Characteristics
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
fsys_xtal
15.6
33.3
35.0
MHz
O1.1
Oscillator start-up time
tup_osc
—
10
ms
O1.2
Table 9. RTC Oscillator Electrical Characteristics
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
RTC_XTAL frequency
frtc_xtal
—
32.768
—
kHz
O2.1
Table 10. System PLL Specifications
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
fsys_xtal
(1)
1 The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU
(core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies.
15.6
33.3
35.0
MHz
O3.1
SYS_XTAL cycle time
tsys_xtal
66.6
30.0
28.5
ns
O3.2
SYS_XTAL clock input jitter
tjitter
(2)
2 This represents total input jitter—short term and long term combined—and is guaranteed by design. Two different
types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected.
Systemic jitter is passed into and through the PLL to the internal clock circuitry.
—
150
ps
O3.3
System VCO frequency
fVCOsys
(1)
250
533
800
MHz
O3.4
System PLL relock time
tlock
(3)
3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
—
100
μsO3.5
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