参数资料
型号: SPC560B50L5C5E0R
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-144
文件页数: 24/74页
文件大小: 971K
代理商: SPC560B50L5C5E0R
SPC560Bx, SPC560Cx
Electrical characteristics
Doc ID 14619 Rev 4
4.9
Power management electrical characteristics
4.9.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the
common I/O supply VDD. The following supplies are involved:
HV—High voltage external power supply for voltage regulator module. This must be
provided externally through VDD power pin.
BV—High voltage external power supply for internal ballast module. This must be
provided externally through VDD_BV power pin. Voltage values should be aligned with
VDD.
LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is
generated by the internal voltage regulator but provided outside to connect stability
capacitor. It is further split into four main domains to ensure noise isolation between
critical LV modules within the device:
LV_COR—Low voltage supply for the core. It is also used to provide supply for
FMPLL through double bonding.
LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double
bonding.
1.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2.
All values need to be confirmed during device validation.
3.
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the
device reference manual).
4.
CL includes device and package capacitance (CPKG <5 pF).
5.
The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
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