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参数资料
型号： SPC560B50L5C5E0R
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封装： 20 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-144
文件页数： 39/74页
文件大小： 971K
代理商： SPC560B50L5C5E0R
SPC560Bx, SPC560Cx
Electrical characteristics
Doc ID 14619 Rev 4
44/74
4.15
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to
generate a fast system clock from the main oscillator driver.
Table 35.
Slow external crystal oscillator (32 kHz) electrical characteristics
Symbol
C
Parameter
Conditions(1)
Value(2)
Unit
Min
Typ
Max
fSXOSC
SR — Slow external crystal oscillator frequency
—
32
32.768
40
kHz
gmSXOSC
CC —
Slow external crystal oscillator
transconductance
VDD = 3.3 V ± 10%,
PAD3V5V = 1
TBD
mA/V
VDD = 5.0 V ± 10%
PAD3V5V = 0
TBD
VDD = 3.3 V ± 10%,
PAD3V5V = 1
TBD
VDD = 5.0 V ± 10%,
PAD3V5V = 0
TBD
VSXOSC
CC T Oscillation amplitude
—
2.1
—
V
ISXOSCBIAS CC T Oscillation bias current
—
TBD
A
ISXOSC
CC T Slow external crystal oscillator consumption
—
8
A
TSXOSCSU CC T Slow external crystal oscillator start-up time
—
2(3)
s
1.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2.
All values need to be confirmed during device validation.
3.
Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal
Table 36.
FMPLL electrical characteristics
Symbol
C
Parameter
Conditions(1)
Value(2)
Unit
Min Typ Max
fPLLIN
SR — FMPLL reference clock(3)
—4
—
64
MHz
Δ
PLLIN
SR — FMPLL reference clock duty cycle(3)
—40
—
60
%
fPLLOUT CC P FMPLL output clock frequency
—
16
—
64
MHz
fCPU
SR — System clock frequency
—
64(4) MHz
fFREE
CC P Free-running frequency
—
20
—
150 MHz
tLOCK
CC P FMPLL lock time
Stable oscillator (fPLLIN = 16 MHz)
40
100
s
Δt
LTJIT
CC — FMPLL long term jitter
fPLLIN = 16 MHz (resonator),
fPLLCLK @ 64 MHz, 4000 cycles
—
10
ns
IPLL
CC C FMPLL consumption
TA = 25 °C
—
4
mA
1.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2.
All values need to be confirmed during device validation.
3.
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional
mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.
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