参数资料
型号: SPC560P50L3CEFBR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, ROHS COMPLIANT, LQFP-100
文件页数: 7/31页
文件大小: 411K
代理商: SPC560P50L3CEFBR
SPC560P44Lx, SPC560P50Lx
Overview of the SPC560Px
Doc ID 13950 Rev 5
The PLL has the following major features:
Input clock frequency from 4 MHz to 40 MHz
Voltage Controlled Oscillator (VCO) range from 256 MHz to 512 MHz
Reduced Frequency Divider (RFD) for reduced frequency operation without forcing the
PLL to relock
Frequency modulated PLL
Modulation enabled/disabled through software
Triangle wave modulation
Programmable modulation depth (±0.25 % to ±4 % deviation from center frequency)
Programmable modulation frequency dependent on reference frequency
Self-cLocked Mode (SCM) operation
3.2.9
Main oscillator
The main oscillator provides these features:
Input frequency range: 4-40 MHz
Crystal input mode or oscillator input mode
PLL reference
3.2.10
Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.
The RC Oscillator provides these features:
Nominal frequency 16MHz
+/-5 % variation over voltage and temperature after process trim
Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the PLL
RC oscillator is used as the default system clock during startup
3.2.11
Periodic Interrupt Timer Module (PIT)
The PIT module implements these features:
Up to four general purpose interrupt timers
32-bit counter resolution
Clocked by system clock frequency
Each channel can be used as trigger for a DMA request
3.2.12
System Timer Module (STM)
The STM module implements these features:
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode
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