参数资料
型号: SPC560P50L5CEFBY
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, ROHS COMPLIANT, LQFP-144
文件页数: 17/31页
文件大小: 411K
代理商: SPC560P50L5CEFBY
Overview of the SPC560Px
SPC560P44Lx, SPC560P50Lx
Doc ID 13950 Rev 5
These are the key parameters of the junction temperature sensor:
Nominal temperature range from –40 °C to 150 °C
Calibrated sensor accuracy:
±10 °C, –40 to 25 °C ambient
±7 °C, 25 to 125 °C ambient
3.2.28
Nexus Development Interface (NDI)
The NDI block provides real-time development support capabilities for the SPC560Px Power
Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This
development support is supplied for MCUs without requiring external address and data pins
for internal visibility. The NDI block is an integration of several individual Nexus blocks that
are selected to provide the development support interface for this device. The NDI block
interfaces to the host processor and internal busses to provide development support as per
the IEEE-ISTO 5001-2003 Class 2+ standard. The development support provided includes
access to the MCUs internal memory map and access to the processors internal registers
during run time.
The Nexus Interface provides the following features:
Configured via the IEEE 1149.1
All Nexus port pins operate at VDDIO (no dedicated power supply)
Nexus 2+ features supported
Static debug
Watchpoint messaging
Ownership trace messaging
Program trace messaging
Real time read/write of any internally memory mapped resources through JTAG
pins
Overrun control, which selects whether to stall before Nexus overruns or keep
executing and allow overwrite of information
Watchpoint triggering, watchpoint triggers program tracing
Auxiliary output port
4 MDO (Message Data Out) pins
MCKO (Message Clock Out) pin
2 MSEO (Message Start/End Out) pins
–EVTO (Event Out) pin
Auxiliary Input Port
–1 EVTI (Event In) pin
3.2.29
IEEE 1149.1 JTAG controller
The JTAG Controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.
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