参数资料
型号: SPC560P50L5CEFBY
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, ROHS COMPLIANT, LQFP-144
文件页数: 3/31页
文件大小: 411K
代理商: SPC560P50L5CEFBY
SPC560P44Lx, SPC560P50Lx
Overview of the SPC560Px
Doc ID 13950 Rev 5
3.2
Feature details
3.2.1
High performance e200z0 core processor
The e200z0 Power Architecture core provides the following features:
High performance e200z0 core processor for managing peripherals and interrupts
Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
Harvard architecture
Variable Length Encoding (VLE), allowing mixed 16-bit and 32-bit instructions
Results in smaller code size footprint
Minimizes impact on performance
Branch processing acceleration using lookahead instruction buffer
Load/store unit
1-cycle load latency
Misaligned access support
No load-to-use pipeline bubbles
Thirty-two 32-bit General Purpose Registers (GPRs)
Separate instruction bus and load/store bus Harvard architecture
Hardware vectored interrupt support
Reservation instructions for implementing read-modify-write constructs
Long cycle time instructions, except for guarded loads, do not increase interrupt latency
Extensive system development support through Nexus debug port
Non-maskable interrupt support
3.2.2
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic will select the higher priority master and grant it ownership of the slave port.
All other masters requesting that slave port will be stalled until the higher priority master
completes its transactions. Requesting masters will be treated with equal priority and will be
granted access to a slave port in round-robin fashion, based upon the ID of the last master
to be granted access.
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