参数资料
型号: SPC560P50L5CEFBY
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, ROHS COMPLIANT, LQFP-144
文件页数: 24/31页
文件大小: 411K
代理商: SPC560P50L5CEFBY
Revision history
SPC560P44Lx, SPC560P50Lx
Doc ID 13950 Rev 5
7
Revision history
Table 5.
Document revision history
Date
Revision
Description
12-Nov-2009
1
Initial release.
16-May-2009
2
Added 64-pin in pin muxing, pin mapping and mechanical data.
13-Jun-2009
3
Removed 64-pin, changed the contents and added new RPNs.
27-Feb-2009
4
Formatting and style corrections.
Revised the document to reflect the correct information on the two available
devices (with 384 KB and 512 KB flash memory).
Replaced erroneous 60 MHz core speed with 64 MHz core speed.
In the DSPI section, changed the number of chip selects (was up to 4, is up
to 8).
Added the commercial product code structure.
Removed the feature list (in Section 3.2).
Added a revision history.
27-Nov-2009
5
Editorial changes.
In the block diagram:
– Removed the Nexus block from the core.
– Moved the JTAG block to outside the core.
– Move the ECSM block.
In the device comparison table:
– Added entries for Safety Channel and Data Flash
– Changed the flash memory information to indicate only the program flash
memory
– Added “Full Feature“ and “Airbag“ customization.
In the feature list:
– Replaced “32-bit Power Architecture Book E CPU” with “32-bit Power
Architecture
Book III-E CPU”.
– Specified LIN 2.1 in communications interfaces feature.
– Updated “Available memory” sub-bullet to “As much as 512 KB on-chip
code flash memory with additional 64 KB for EEPROM emulation (Data
Flash), with ECC, with erase/program controller”.
– Changed ADC sub-bullet to “Two × 15 input channels, four channels
shared among the two A/D converters”.
In the feature details:
– In the ADC section, changed “TUE <1.5 LSB” to “TUE <3 LSB”.
– In the temperature sensor section, changed “Accuracy of the sensor ±5
°C (tbc)” to “Calibrated sensor accuracy ±5 °C”
– In the JTAG section, removed sentence “The size of the boundary scan
register is parameterized to support a variety of boundary scan chain
lengths.”
– In the CTU section, changed CTU queue bullet to “4 independent result
queues (2 × 16 entries, 2 × 4 entries)”.
In the order codes table:
– Renamed the “Flash (KB)“ heading column in “Code Flash / Data Flash
(EE) (KB)“.
– Replaced the value of RAM from 32 to 36KB in the last four rows.
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