- 您现在的位置：买卖IC网 > PDF目录2017 > SPC5634MF1MLQ80 (Freescale Semiconductor)IC MCU FLASH 1.5M 94K 144-LQFP PDF资料下载
参数资料
| 型号： | SPC5634MF1MLQ80 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 2/122页 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 1.5M 94K 144-LQFP |
| 标准包装： | 60 |
| 系列： | MPC56xx Qorivva |
| 核心处理器： | e200z3 |
| 芯体尺寸： | 32-位 |
| 速度： | 80MHz |
| 连通性： | CAN，EBI/EMI，LIN，SCI，SPI，UART/USART |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 114 |
| 程序存储器容量： | 1.5MB（1.5M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 94K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.25 V |
| 数据转换器： | A/D 32x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 150°C |
| 封装/外壳： | 144-LQFP |
| 包装： | 托盘 |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页
MPC5634M Microcontroller Data Sheet, Rev. 9
Overview
Freescale Semiconductor
10
Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a
supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches.
Prefetched instructions are placed into an instruction buffer capable of holding six instructions.
Branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the
instruction decode stage, allowing the branch target to be prefetched early. When a branch is detected at the instruction buffer,
a prediction may be made on whether the branch is taken or not. If the branch is predicted to be taken, a target fetch is initiated
and its target instructions are placed in the instruction buffer following the branch instruction. Many branches take zero cycle
to execute by using branch folding. Branches are folded out from the instruction execution pipe whenever possible. These
include unconditional branches and conditional branches with condition codes that can be resolved early.
Conditional branches which are not taken and not folded execute in a single clock. Branches with successful target prefetching
which are not folded have an effective execution time of one clock. All other taken branches have an execution time of two
clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign
extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow
effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore
operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be
optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power
Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move,
integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching.
Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple
interrupt sources to have unique interrupt handlers invoked with no software overhead.
The hardware floating-point unit utilizes the IEEE-754 single-precision floating-point format and supports single-precision
floating-point operations in a pipelined fashion. The general purpose register file is used for source and destination operands,
thus there is a unified storage model for single-precision floating-point data types of 32 bits and the normal integer type.
Single-cycle floating-point add, subtract, multiply, compare, and conversion operations are provided. Divide instructions are
multi-cycle and are not pipelined.
The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware SIMD operations and supports a
full complement of dual integer arithmetic operation including Multiply Accumulate (MAC) and dual integer multiply (MUL)
in a pipelined fashion. The general purpose register file is enhanced such that all 32 of the GPRs are extended to 64 bits wide
and are used for source and destination operands, thus there is a unified storage model for 32
32 MAC operations which
generate greater than 32-bit results.
The majority of both scalar and vector operations (including MAC and MUL) are executed in a single clock cycle. Both scalar
and vector divides take multiple clocks. The SPE APU also provides extended load and store operations to support the transfer
of data to and from the extended 64-bit GPRs. This SPE APU is fully binary compatible with e200z6 SPE APU used in
MPC5554 and MPC5553.
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This enables the classic Power
Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16- and 32-bit
instructions. This results in a significantly smaller code size footprint without noticeably affecting performance. The Power
Architecture instruction set and VLE instruction set are available concurrently. Regions of the memory map are designated as
PPC or VLE using an additional configuration bit in each of Table Look-aside Buffers (TLB) entries in the MMU.
The CPU core is enhanced by the addition of two additional interrupt sources; Non-Maskable Interrupt and Critical Interrupt.
These two sources are routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing completely
the Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled, except by reset. The non-maskable
Interrupt is, as the name suggests, completely un-maskable and when asserted will always result in the immediate execution of
the respective interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable. The Critical Interrupt
is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the CPU and is guaranteed
to be recoverable (code execution may be resumed from where it stopped).
相关PDF资料 |
PDF描述 |
|---|---|
| SPL505YC256BT | IC CLOCK CK505 BEARLAKE 56TSSOP |
| SPL505YC264BT | IC CLOCK CK505 BEARLAKE 64TSSOP |
| SSM2603CPZ-R2 | IC CODEC AUDIO LOW POWER 28LFCSP |
| SSM2604CPZ-REEL | IC AUDIO CODEC LP 20-LFCSP |
| SY100E195JY TR | IC DELAY LINE 128TAP 28-PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SPC5634MF1MLU60 | 功能描述:32位微控制器 - MCU 1.5M FLASH 94K RAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| SPC5634MF1MLU80 | 功能描述:32位微控制器 - MCU 1.5M FLASH 94K RAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| SPC5634MF1MMG60 | 功能描述:32位微控制器 - MCU 1.5M FLASH 94K RAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| SPC5634MF1MMG80 | 功能描述:32位微控制器 - MCU 1.5M Flash,94K RAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| SPC5634MF2MLQ80 | 制造商:Freescale Semiconductor 功能描述:SPC5634MF2MLQ80 - Bulk |
发布紧急采购，3分钟左右您将得到回复。