
SPC563M64
Electrical characteristics
Doc ID 14642 Rev 6
—
CC
C
4MHz
5
30
pF
8MHz
5
26
12 MHz
5
23
16 MHz
5
19
20 MHz
5
16
tlpll
CC
C
—
200
μs
tdc
CC
C
Duty cycle of reference
—40
60
%
fLCK
CC
C
Frequency LOCK range
—
–6
6
% fsys
fUL
CC
C
Frequency un-LOCK range
—
–18
18
% fsys
fCS
fDS
CC
C
Modulation Depth
Center spread
±0.25
±4.0
%fsys
C
Down Spread
–0.5
–8.0
fMOD
CC
C
Modulation frequency(17)
—
100
kHz
1.
All values given are initial design targets and subject to change. The values in the table are simulated at (VDDPLL =1.14 V to
1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH)
2.
Considering operation with PLL not bypassed.
3.
fVCO is calculated as follows:
— In Legacy Mode fVCO = (fcrystal/(PREDIV+1))*(4*(MFD+4))
— In Enhanced Mode fvco = (fcrystal/(EPREDIV+1))*(EMFD+4)
4.
All internal registers retain data at 0 Hz.
5.
“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.
6.
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR
window.
7.
fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced
mode.
8.
This value is determined by the crystal manufacturer and board design.
9.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER
percentage for a given interval.
10. Proper PC board layout procedures must be followed to achieve specifications.
11. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either
fCS or fDS (depending on whether center spread or down spread modulation is enabled).
12. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
PLL, load capacitors should not exceed these limits. For a 20 MHz crystal the maximum load should be 17 pF.
13. Proper PC board layout procedures must be followed to achieve specifications.
14. This parameter is guaranteed by design rather than 100% tested.
15. VIHEXT cannot exceed VRC33 in external reference mode.
16. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
17. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50kHz.
Table 26.
PLLMRFM electrical specifications(1) (continued)
Symbol
C
Parameter
Conditions
Value
Unit
min
max