参数资料
型号: SPEAR300-2
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 333 MHz, RISC MICROCONTROLLER, PBGA289
封装: 15 X 15 MM, 1.70 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, LFBGA-289
文件页数: 38/83页
文件大小: 1027K
代理商: SPEAR300-2
SPE
Ar300
Pin
de
scr
ip
tion
Doc
ID
1
6324
R
e
v
2
4
3
/83
PL_GPIO_73/A17
0
A7
CLD7
G8_7 (out)
CLD7
0
CLD7
A7
Reserved
CLD7
Reserved
CLD7
PL_GPIO_72/B16
0
A8
CLD8
IT0
CLD8
IT0
CLD8
IT0
Reserved
CLD8
Reserved
CLD8
PL_GPIO_71/D14
0
A9
CLD9
IT1
CLD9
IT1
CLD9
IT1
Reserved
CLD9
Reserved
CLD9
PL_GPIO_70/C15
0
A10
CLD10
IT2
CLD10
IT2
CLD10
IT2
Reserved
CLD10
Reserved
CLD10
PL_GPIO_69/A16
0
A11
CLD11
IT3
CLD11
IT3
CLD11
IT3
Reserved
CLD11
Reserved
CLD11
PL_GPIO_68/B15
0
A12
CLD12
IT4
CLD12
IT4
CLD12
IT4
Reserved
CLD12
Reserved
CLD12
PL_GPIO_67/C14
0
A13
CLD13
IT5
CLD13
IT5
CLD13
IT5
Reserved
CLD13
Reserved
CLD13
PL_GPIO_66/E13
0
A14
CLD14
IT6
CLD14
IT6
CLD14
IT6
Reserved
CLD14
Reserved
CLD14
PL_GPIO_65/B14
0
A15
CLD15
IT7
CLD15
IT7
CLD15
IT7
Reserved
CLD15
Reserved
CLD15
PL_GPIO_64/D13
0
A16
CLD16
SPI_I2C4
CLD16
SPI_I2C4
CLD16
SPI_I2C4
Reserved
CLD16
Reserved
CLD16
PL_GPIO_63/C13
0
A17
CLD17
SPI_I2C5
CLD17
SPI_I2C5
CLD17
SPI_I2C5
Reserved
CLD17
Reserved
CLD17
PL_GPIO_62/A15
0
A18
CLD18
SPI_I2C6
CLD18
SPI_I2C6
CLD18
SPI_I2C6
Reserved
CLD18
Reserved
CLD18
PL_GPIO_61/E12
0
A19
CLD19
SPI_I2C7
CLD19
SPI_I2C7
CLD19
SPI_I2C7
/DOUT
SPI_I2C7
/DOUT
Reserved
CLD19
Reserved
CLD19
PL_GPIO_60/A14
0
A20
CLD20
TDM_
SYNC4
CLD20
TDM_
SYNC4
CLD20
TDM_
SYNC4
TDM_
SYNC4
Reserved
CLD20
Reserved
CLD20
PL_GPIO_59/B13
0
A21
CLD21
TDM_
SYNC5
CLD21
TDM_
SYNC5
CLD21
TDM_
SYNC5
TDM_
SYNC5
Reserved
CLD21
Reserved
CLD21
PL_GPIO_58/D12
CL
A22
CL
TDM_
SYNC6
CLD22
TDM_
SYNC6
CLD22
TDM_
SYNC6
CL
Reserved
CLD22
Reserved
CLD22
PL_GPIO_57/E11
AL
A23
AL
TDM_
SYNC7
CLD23
TDM_
SYNC7
CLD23
TDM_
SYNC7
AL
Reserved
CLD23
Reserved
CLD23
PL_GPIO_56/C12
/W
ROW7
/W
ROW7
VSYNC_1
ROW7
PL_GPIO_55/A13
/R
/G
/R
ROW8
/R
ROW8
HSYNC_1
ROW8
PL_GPIO_54/E10
0
CLAC
G10_9
CLAC
G10_9
CLAC
G10_9
CLAC
G10_9
CLAC
PL_GPIO_53/D11
0
CLCP
G10_8
CLCP
G10_8
CLCP
G10_8
CLCP
G10_8
CLCP
PL_GPIO_52/B12
0
CLFP
G10_7
CLFP
G10_7
CLFP
G10_7
CLFP
G10_7
CLFP
Table 11.
PL_GPIO multiplexing scheme (continued)
PL_GPIO_# /
ball number
Configuration mode (enabled by RAS register 2)
Alternate
function
(enabled
by RAS
register 1)
1
2
3
4
5
6789
10
11
12
13
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