参数资料
型号: SPI-324P-O4-N1
厂商: Lattice Semiconductor Corporation
文件页数: 16/23页
文件大小: 0K
描述: IP PHY LAYER BRIDGE SPI3-4 ORCA4
标准包装: 1
系列: *
其它名称: SPI324PO4N1
Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Receive Interface AC Timing
Table 7. Receive Interface Timing
Bridge Core User’s Guide
Symbol
tS renb
tH renb
tP rdat
tP rprty
tP rsop
tP reop
tP rmod
tP rerr
tP rval
tP rsx
Description
RFCLK Frequency
RFCLK Duty Cycle
RENB Set-up time to RFCLK
RENB Hold time to RFCLK
RFCLK High to RDAT Valid
RFCLK High to RPRTY Valid
RFCLK High to RSOP Valid
RFCLK High to REOP Valid
RFCLK High to RMOD Valid
RFCLK High to RERR Valid
RFCLK High to RVAL Valid
RFCLK High to RSX Valid
Min.
40
2
0.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Max.
104
60
6
6
6
6
6
6
6
6
Units
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 8. Receive Physical Timing
RFCLK
tSrenb
tHrenb
RENB
tPrdat
RDAT[31:0]
tPrprty
RPRTY
tPrmod
RMOD
tPrsop
RSOP
tPreop
REOP
tPrerr
RERR
tPrval
RVAL
tPrsx
RSX
Notes on Receive I/O Timing:
1. When a set-up time is speci?ed between an input and a clock, the set-up time is the time in nanoseconds from
the 1.4V point of the input to the 1.4V point of the clock.
2. When a hold time is speci?ed between an input and a clock, the hold time is the time in nanoseconds from the
1.4V point of the clock to the 1.4V point of the input.
3. Output propagation delay time is the time in nanoseconds from the 1.4V point of the reference signal to the
1.4V point of the output.
4. Maximum output propagation delays are measured with a 30pF load on the outputs.
16
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