- 您现在的位置：买卖IC网 > PDF目录1245 > SPI-324P-O4-N1 (Lattice Semiconductor Corporation)IP PHY LAYER BRIDGE SPI3-4 ORCA4 PDF资料下载
参数资料
| 型号： | SPI-324P-O4-N1 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 20/23页 |
| 文件大小： | 0K |
| 描述： | IP PHY LAYER BRIDGE SPI3-4 ORCA4 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | SPI324PO4N1 |
Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Bridge Core User’s Guide
6. In the Implementation Options, set the following:
– Fanout guide: 1000
– Enable FSM Compiler
– Enable Resource Sharing
– Set the global frequency constraint to 104MHz.
7. Select run.
Synthesis Using LeonardoSpectrum
To synthesize the Quad SPI-3 to SPI-4 Link Layer Bridge solution LeonardoSpectrum in one step, go to the direc-
tory “eval\synthesis exemplar” and enter “run_syn.bat” (for PC). A top-level EDIF for the application will be pro-
duced. Users may use run_syn.bat as a guide and template if they are creating their own unique system-level
project solution.
The following step-by-step procedure may also be executed. Note that the step-by step ?ow results vary from those
obtained with the scripted ?ow due to possible small differences in options between both ?ows.
The step-by-step procedure provided below describes how to run synthesis using LeonardoSpectrum.
1. Create a new working directory for synthesis.
2. Launch the LeonardoSpectrum synthesis tool.
3. Start a new project and select Lattice device technology ORCA-4E.
4. Select Input tab, set the Working Directory path pointed to the source directory.
5. Open the speci?ed ?les in the following order:
source/ exemplar/orca4_leonardo.v
source/top/qspi3_link_params.v
source/ exemplar/rfclk_pll_bo.v
source/ exemplar/rfclk_hpll_bo.v
source/ exemplar/mycore.v
source/ exemplar/sysbus_fpsc.v
source/top/spi_324l_o4_1_001.v
source/top/fpga_io.v
source/top/orspi.v
6. Select orspi.v, use the right click button on your mouse, and choose from the list “Make orspi.v Top of the
Design”
7. In the Constraints tab, set Clock Frequency as 104MHz.
8. Set the Synthesis Directory, created in step 1, as the path where you would like to save the output netlist.
9. Specify an EDIF netlist ?lename for the output ?le. This top-level EDIF netlist will be used during Place and
Route.
10. Select Run Flow
Place and Route
Once the EDIF netlist is generated, the next step is to map, place and route the design.
The step-by-step procedure provided below explains how to run an EDIF based ?ow through place and route using
ispLEVER Project Navigator.
20
相关PDF资料 |
PDF描述 |
|---|---|
| SPN02SVBN-RC | CONN JUMPER SHORTING 2MM GOLD |
| SPN02SVEN-RC | CONN JUMPER SHORTING 2MM GOLD |
| SPN02SXCN-RC | CONN JUMPER SHORTING 2MM GOLD |
| SPT711XPFCE | CARD TELEPHONY FARM CRD 711X |
| SPUSB1AJT | SURGE SUPPRESOR USB 12OHM SC70-6 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SPI-333-34AB | 制造商:SANYO Semiconductor Co Ltd 功能描述: |
| SPI-335-34 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:Ultraminiature photoreflector (single-transistor type) |
| SPI-336-99-T1 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:Ultraminiature photoreflector supporting reflow soldering Single transistor type |
| SPI3501UH | 制造商:SPI 制造商全称:SPI 功能描述:350 Watts EPS12V 1U Switching Power Supply |
| SPI3501UH-B204 | 制造商:Sparkle Power Inc 功能描述:POWER SUPPLY,SWITCHING,ENCLOSED,1U,350 WATT,ATX/EPS,PFC,(2)1 |
发布紧急采购，3分钟左右您将得到回复。