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| 型号： | SPL11A |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SPL11A PROGRAMMING GUIDE |
| 中文描述： | SPL11A节目指南 |
| 文件页数： | 11/42页 |
| 文件大小： | 1865K |
| 代理商： | SPL11A |
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SPL11A PROGRAMMING GUIDE
PRELIMINARY
4 CPU Clock Control
4.1
Clock Source Control
There are two groups of clock sources controlled by two clock option pins:
1. High-speed clock sources (HSCK): PLL / ROSC.
2. Low-speed clock sources (LSCK): 32768Hz oscillator / 32768 Crystal.
They are selected by pin option (OTP version) or mask option (ROM version). In OTP version: HSCK
(High-speed clock) can be selected to PLL or Rosc via
HCKOPT pin
(pull-high for PLL; pull-low for
ROSC (default)). In ROM version: HSCK (High-speed clock) can be selected to PLL or Rosc via
mask
option.
In OTP version: LSCK (Low-speed clock) can be selected to X32K or R32K by
LCKOPT pin
(pull high
for R32K; pull-low for X32K (default)). In ROM version: LSCK (Low-speed clock) can be selected to
X32K or R32K via
mask option
.
4.1.1 Clock sources combination (OTP)
HCKOPT
LCKOPT
ROSC/X32K
0
0
ROSC/R32K
0
1
PLL/X32K
1
X
Note
Note: No PLL/R32K combination, it is mapped to PLL/X32K mode
4.2
CPU Clock Control Register
4.2.1
P_05H_CPU_CLK ($0005):
set CPU clock
$0005
b7
b6
b5
b4
b3
b2
b1
b0
Name
-
-
-
-
-
CPUCK2 CPUCK1 CPUCK0
R/W
-
-
-
-
-
R/W
R/W
R/W
Default
-
-
-
-
-
0
0
0
Sunplus Technology Co., Ltd.
PAGE 11
V0.1 – OCT. 23, 2002
Bit
Mode
CPUCK=HSCK/16
CPUCK=HSCK/8
CPUCK=HSCK/4
CPUCK=HSCK/2
CPUCK=LSCK(32768)
b2
(CPUCK2)
0
0
0
0
1
b1
(CPUCK1)
0
0
1
1
X
b0
(CPUCK0)
0
1
0
1
X
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