参数资料
型号: SPL11A
厂商: Electronic Theatre Controls, Inc.
英文描述: SPL11A PROGRAMMING GUIDE
中文描述: SPL11A节目指南
文件页数: 6/42页
文件大小: 1865K
代理商: SPL11A
SPL11A PROGRAMMING GUIDE
PRELIMINARY
2 Introduction
2.1
General Description
SPL11A, a 8-bit LCD micro-controller, contains LCD-drivers, one-time programmable (OTP) ROM,
SRAM, I/O, timer/counter, PLL, audio/remote control out, resistor to frequency converter (RFC) function
in a single chip. The SPL11A is designed to drive LCD directly and perform efficient controller function
as well as arithmetic function. With the on-chip crystal oscillator, real time clock can be easily achieved.
For power savings, several power-down modes are controllable by software programming. The
SPL11A is designed to be used in low-power electronic products such as remote controller, home
appliance, calculator, and general LCD controller, etc.
2.2
Feature
Built-in Sunplus 8-bit CPU (Compatible with full 6502 instruction sets)
Working voltage: 2.4V ~ 5.5V
Maximum CPU speed: 4MHz @ 2.4V in ROSC mode
8K-byte EPROM with parallel programming & verification
128 bytes SRAM
48 bytes dual-port SRAM for LCD buffers
LCD bias: 1/2 bias, 1/3 bias, 1/4 bias
LCD dots: 12x30 (360 dots), 11x30 (330 dots), 10x30 (300 dots), 9x32 (288 dots), 8x32 (256 dots),
5x32 (160 dots), 4x32 (128 dots), and 3x32 (96 dots)
A 16-bit re-loadable timer/counter
An 8-pin IOA (Input with pull-high, input with pull low, floating, output, N open drain, P open drain)
IOB Inputs with key wakeup function & pull-low (4 inputs pins shared with LCD segments)
Dual clock PLL/R-oscillator & 32768
CPU Clock: PLL/2, PLL/4, PLL/8, PLL/16, 32768
PLL clock = 32768 * 37 * 4 = 4,849,664Hz; Maximum CPU clock in PLL clock mode: 4849664/2 =
2,424,832Hz
Four Operating modes: Operating, Wait, Halt, and Standby modes
Interrupt sources: 37.9K/N, 32768/N, TMO, EXT0, EXT1, T2Hz, and KEYC.
Seven wakeup sources
Built-in RFC (Resistor to Frequency Converter) function
Reset flags: watchdog, error address, power-on, external reset, low voltage
Sunplus Technology Co., Ltd.
PAGE 6
V0.1 – OCT. 23, 2002
Watchdog reset and error-address reset are always enabled and will reset CPU if these events
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