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| 型号： | SPL11A |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SPL11A PROGRAMMING GUIDE |
| 中文描述： | SPL11A节目指南 |
| 文件页数： | 21/42页 |
| 文件大小： | 1865K |
| 代理商： | SPL11A |
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SPL11A PROGRAMMING GUIDE
PRELIMINARY
6.1.2 P_0FH_SYS_SWITCH ($000F)
System state read back
READ FROM P_0FH_SYS_SWITCH ($000F)
BIT
b0
STATUS
0:HSCk is still ON
1:HSCK is OFF
0:LSCK is in weak mode
1:LSCK is in strong mode
0:Wakeup to CPU-Reset
1:Wakeup to next-instruction
N/A
N/A
N/A
N/A
N/A
b1
b2
b3
b4
b5
b6
b7
Description:
1. The P_0FH_SYS_SWITCH ($000F)
is a two-stage control port. A successful writing of the first
stage makes the 2
nd
stage to be valid. Firmware must write to setup this port in the 2
nd
stage.
The b7 is the data bit for the second stage writing operation.
2. The X32K crystal initially starts running at strong mode and will change to weak mode after
250ms automatically when X32K crystal is turned on (This will not change the setting in $0F
weak/strong mode setting). Program will be executed after crystal oscillation is stabilized.
3. Using PLL for IR or Timer source, user’s program must delay at least 8ms for the stabilization of
the PLL circuit at the moment of PLL start running.
4. If no any wakeup source is configured, it is unable to enter WAIT/HALT/STANDBY mode.
5. Setting WAIT/HSCK/LSCK control bit to enter WAIT/HALT/STANDBY mode.
6. Waking up from standby mode, the
P_05H_CPU_CLK ($0005)
will be reset to the default value
(HSCK/16). In wait and halt modes, the
P_05H_CPU_CLK ($0005)
will remain the same
state.
Sunplus Technology Co., Ltd.
PAGE 21
V0.1 – OCT. 23, 2002
Mode
Description
Action
Operating
Normal operating mode
---
WAIT
CPU OFF / all clock sources
are still ON
Configure $0F register to set WAIT mode.
HALT
CPU OFF/ HSCK OFF, 32768
still ON
Configure $0F register to stop HSCk when
CPU clock is HSCK.
STANDBY
CPU OFF/All clock-sources
OFF
Configure $0F register to stop LSCK
regardless where the CPU clock comes from
HSCK or LSCK.
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