参数资料
型号: SPL505YC264ATT
元件分类: 时钟产生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PDSO64
封装: 6 X 17 MM, LEAD FREE, MO-153, TSSOP-64
文件页数: 10/27页
文件大小: 314K
代理商: SPL505YC264ATT
SPL505YC264BT
Rev 1.4 May 21, 2007
Page 18 of 27
.
PD_RESTORE
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#
LOW, the CY505 will initiate a full reset. The results of this will
be that the clock chip will emulate a cold power on start and
go to the ‘Latches Open’ state. If the PD_RESTORE bit is set
to a ‘1’ then the configuration is stored upon PWRDWN#
asserted LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to
a ‘1’ then the PD_RESTORE bit must be ignored. In other
words, in Intel iAMT mode, PWRDWN# reset is not allowed.
Figure 7. CK_PWRGD Timing Diagram
Table 6. Output Driver Status during PCI-STOP# and CPU-STOP#
PCI_STOP# Asserted
CPU_STOP# Asserted
SMBus OE Disabled
Single-ended Clocks Stoppable
Driven Low
Running
Driven Low
Non Stoppable
Running
Differential Clocks
Stoppable
Clock Drive High
Clock# Driven Low
Clock Drive High
Clock# Driven Low
Driven Low or 20K
pulldown
Non Stoppable
Running
Table 7. Output Driver Status
All Single-ended Clocks
All Differential Clocks except
CPU1
w/o Strap
w/Strap
Clock
Clock#
Clock
Clock#
Latches Open State
Low
Hi-Z
Low or 20K pulldown Low
Powerdown
Low
Hi-Z
Low or 20K pulldown Low
M1
Low
Hi-Z
Low or 20K pulldown Low
Running
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