参数资料
型号: SPL505YC264ATT
元件分类: 时钟产生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PDSO64
封装: 6 X 17 MM, LEAD FREE, MO-153, TSSOP-64
文件页数: 7/27页
文件大小: 314K
代理商: SPL505YC264ATT
SPL505YC264BT
Rev 1.4 May 21, 2007
Page 15 of 27
PD# Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function. When the
CPU_STP# pin is asserted, all CPU outputs that are set with
the SMBus configuration to be stoppable via assertion of
CPU_STP# are stopped within two to six CPU clock periods
after being sampled by two rising edges of the internal CPUC
clock. The final states of the stopped CPU signals are CPUT
= HIGH and CPUC = LOW.
PD#
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
Figure 3. PD Assertion Timing Waveform
DOT96C
PD#
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
USB, 48MHz
DOT96T
SRCT 100MHz
Tstable
<1.8ms
PCI, 33MHz
REF
Tdrive_PW RDN#
<300S, >200mV
PD Deassertion Timing Waveform
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