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参数资料
| 型号： | SPL505YC264BT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 封装： | 6 X 17 MM, LEAD FREE, MO-153, TSSOP-64 |
| 文件页数： | 2/27页 |
| 文件大小： | 314K |
| 代理商： | SPL505YC264BT |
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SPL505YC264BT
Rev 1.4 May 21, 2007
Page 10 of 27
7
0
PCIF0_STP_CTRL
Allows control of PCIF0 with assertion of PCI_STOP#
0 = Free running PCIF, 1 = Stopped with PCI_STOP#
6
HW_Pin
TME_STRAP
Trusted mode enable strap status, 0 = normal, 1 = no overclocking
5
1
REF_DSC1
REF drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
4
0
TEST_MODE_SEL
Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
3
0
TEST_MODE_ENTRY
Allow entry into test mode
0=Normal operation, 1=Enter test mode
2
1
IO_VOUT2
IO_VOUT[2,1,0]
000 = 0.3V
001 = 0.4V
010 = 0.5V
011 = 0.6V
100 = 0.7V
101 = 0.8V, Default
110 = 0.9V
111 = 1.0V
1
0
IO_VOUT1
0
1
IO_VOUT0
Byte 9 Control Register 9
Byte 10 Control Register 10
Bit
@Pup
Name
Description
7
HW
SRC5_EN_STRAP
Read only bit for SRC5_EN_STRAP
0 = CPU/PCI_STOP enabled, 1 = SRC5 pair enabled
6
1
PLL3_EN
PLL3 Enabled
0 = PLL3 disabled, 1 = PLL3 enabled
5
1
PLL2_EN
PLL2 Enabled
0 = PLL2 disabled, 1 = PLL2 enabled
4
1
SRC_DIV_EN
SRC Divider Enabled
0 = SRC Divider disabled, 1 = SRC Divider enabled
3
1
PCI_DIV_EN
PCI Divider Enabled
0 = PCI Divider disabled, 1 = PCI Divider enabled
2
1
CPU_DIV_EN
CPU Divider Enabled
0 = CPU Divider disabled, 1 = CPU Divider enabled
1
CPU1_STP_CRTL
Allow control of CPU1 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
0
1
CPU0_STP_CRTL
Allow control of CPU0 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
Byte 11 Control Register 11
Bit
@Pup
Name
Description
7
HW
PCI3_CFG1
6
HW
PCI3_CFG0
5
0
25MHz_EN_SE1
25MHz Output Enabled applies to Powerdown / M1
(Only applies when PCI3/CGFG0 strap is set high to enter HW mode 3)
0 = 25MHz disabled in Powerdown / M1
1 = 25MHz enabled in Powerdown / M1; Sticky 1
4
1
RESERVED
Output
SSC
Output
SSC
Output
SSC
0
0 -Def
CPU / SRC / PCI33
Down
USB
NA
--
0
1
CPU
Down
USB
NA
SRC/PCI33
Down
1
0
2
CPU
Center
USB
NA
SRC/PCI33
Down
1
3
CPU
Center
USB/25M
NA
SRC/PCI33
Down
PLL2
PLL3
PCI3/
CGF1
PCI3/
CGF0
Mode
PLL1
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