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参数资料
| 型号： | SPL505YC264BT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 封装： | 6 X 17 MM, LEAD FREE, MO-153, TSSOP-64 |
| 文件页数： | 4/27页 |
| 文件大小： | 314K |
| 代理商： | SPL505YC264BT |
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SPL505YC264BT
Rev 1.4 May 21, 2007
Page 12 of 27
Byte 14 Control Register 14
Bit
@Pup
Name
Description
7
0
CPU_DAF_N7
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The
setting of the FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[C:A] register will be used. When it is set, the frequency ratio
stated in the FSEL[2:0] register will be used
6
0
CPU_DAF_N6
5
0
CPU_DAF_N5
4
0
CPU_DAF_N4
3
0
CPU_DAF_N3
2
0
CPU_DAF_N2
1
0
CPU_DAF_N1
0
CPU_DAF_N0
Byte 15 Control Register 15
Bit
@Pup
Name
Description
7
0
CPU_DAF_N8
See Byte 14 for description
6
0
CPU_DAF_M6
If Prog_CPU_EN is set, the values programmed are in CPU_FSEL_N[8:0]
and CPU_FSEL_M[6:0] will be used to determine the CPU output
frequency. The setting of the FS_Override bit determines the frequency
ratio for CPU and other output clocks. When it is cleared, the same
frequency ratio stated in the Latched FS[C:A] register will be used. When it
is set, the frequency ratio stated in the FSEL[2:0] register will be used
5
0
CPU_DAF_M5
4
0
CPU_DAF_M4
3
0
CPU_DAF_M3
2
0
CPU_DAF_M2
1
0
CPU_DAF_M1
0
CPU_DAF_M0
Byte 16 Control Register 16
Bit
@Pup
Name
Description
7
0
PCI-E_N7
If Prog_SRC_EN is set, the values programmed in SRC_DAF_N[7:0] will
be used to determine the SRC output frequency.
6
0
PCI-E_N6
5
0
PCI-E_N5
4
0
PCI-E_N4
3
0
PCI-E_N3
2
0
PCI-E_N2
1
0
PCI-E_N1
0
PCI-E_N0
Byte 17 Control Register 17
Bit
@Pup
Name
Description
7
0
SMSW_EN
Enable Smooth Switching, 0 = Disabled, 1= Enabled
6
0
SMSW_SEL
Smooth switch select, 0 = CPU_PLL, 1 = SRC_PLL
5
0
RESERVED
4
0
Prog_PCI-E_EN
Programmable PCI-E frequency enable
0 = Disabled, 1= Enabled
3
0
Prog_CPU_EN
Programmable CPU frequency enable
0 = Disabled, 1= Enabled
2
0
RESERVED
1
0
RESERVED
0
RESERVED
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SPL505YC264BTT | 功能描述:时钟发生器及支持产品 CK505 v0.85 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SPL5100PT | 制造商:CHENMKO 制造商全称:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SPL520LLPT | 制造商:CHENMKO 制造商全称:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SPL53-1024 | 制造商:Power-One 功能描述: |
| SPL53-4000 | 制造商:Power-One 功能描述: |
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