参数资料
型号: SPL505YC264BT
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
封装: 6 X 17 MM, LEAD FREE, MO-153, TSSOP-64
文件页数: 9/27页
文件大小: 314K
代理商: SPL505YC264BT
SPL505YC264BT
Rev 1.4 May 21, 2007
Page 17 of 27
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used to synchro-
nously stop and start the PCI outputs while the rest of the clock
generator continues to function. The set-up time for capturing
PCI_STP# going LOW is 10 ns (tSU). (See Figure 5.) The PCIF
clocks will not be affected by this pin if their corresponding
control bit in the SMBus register is set to allow them to be free
running.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level.
DOT96C
DOT96T
CPUC(Free Running)
CPUT(Free Running)
CPUC(Stoppable)
CPUT(Stoppable)
PD#
1.8mS
CPU_STOP#
CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
T su
P C I_S T P #
P C I_ F
P C I
S R C 1 0 0M H z
Figure 5. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F
PCI
SRC 100MHz
Tsu
Tdrive_SRC
Figure 6. PCI_STP# Deassertion Waveform
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