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参数资料
| 型号： | SPL505YC264BTT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 3/27页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK505 BEARLAKE 64TSSOP |
| 标准包装： | 2,000 |
| 类型： | 时钟/频率发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，PCI Express（PCIe） |
| 输入： | 晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:22 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 400MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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SPL505YC26
.................... Document #: 001-03543 Rev *E Page 11 of 27
3
0
CPU2_AMT_EN
2
1
CPU1_AMT_EN
1
HW
PCI-E_GEN2
PCI-E_Gen2 Compliant
0 = non Gen2, 1= Gen2 Compliant
0
1
CPU2_STP_CRTL
Allow control of CPU2 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
Byte 11 Control Register 11
PCIF0/ITP_EN
AMT_EN
CPU2_AMT_EN
CPU1_AMT_EN
Description
x1
0
Reserved
x
1
0
1
CPU1 = M1 Clock
1
0
CPU2 - M1 Clock
1
CPU1 and CPU2 = M1 Clock
Byte 12 Byte Count
Bit
@Pup
Name
Description
7
0
RESERVED
6
0
RESERVED
5
0
BC5
Byte count
4
0
BC4
Byte count
3
1
BC3
Byte count
2
1
BC2
Byte count
1
0
BC1
Byte count
0
1
BC0
Byte count
Byte 13 Control Register 13
Bit
@Pup
Name
Description
7
1
USB_DSC1
USB drive strength control, See Byte 18 for more setting
0 = Low, 1= High
6
1
PCI/PCIF_DSC1
PCI drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
5
0
PLL1_Spread
Select percentage of spread for PLL1
0 = 0.5%, 1=1%
4
0
SATA_SS_EN
Enable SATA spread modulation,
0 = Spread Disabled 1 = Spread Enabled
3
1
EN_CFG0_SET
By defalult CFG0 pin strap sets the SMBus initial values to select the HW
mode. When this bit is written0, subsequent SMBus accesses is the Lathes
Open state, can overwrite the CFG0 pin setting into the SMBus bits and set
the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5
2
1
SE1/SE2_DSC1
SE1 and SE2 drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
1
RESERVED
0
1
SW_PCI
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
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