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参数资料
| 型号： | SPLC783A |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16COM/80SEG Controller/Driver |
| 中文描述： | 16COM/80SEG控制器/驱动器 |
| 文件页数： | 23/38页 |
| 文件大小： | 2192K |
| 代理商： | SPLC783A |
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SPLC783A
5.16. REGISTER --- IR (Instruction Register) and DR
(Data Register)
Sunplus Technology Co., Ltd.
Proprietary & Confidential
23
MAR. 10, 2005
Version: 1.4
SPLC783A contains two 8-bit registers: Instruction Register (IR)
and Data Register (DR). Using combinations of the RS pin and
the R/W pin selects the IR and DR, see below:
RS
R/W
Fo PARTMNERUseOny
Operation
0
0
IR write (Display clear, etc.)
SunpusConidenia
0
1
Read busy flag (DB7) and Address Counter
(DB0 - DB6)
1
0
DR write (DR to Display data RAM or
Character generator RAM)
1
1
DR read (Display data RAM or Character
generator RAM to DR)
The IR can be written by MPU, but it cannot be read by MPU.
5.17. Busy Flag (BF)
When RS = 0 and R/W = 1, the busy flag is output to DB7. As
the busy flag =1, SPLC783A is in busy state and does not accept
any instruction until the busy flag = 0.
5.18. Address Counter (AC)
The Address Counter assigns addresses to Display Data RAM
and Character Generator RAM. When an instruction for address
is written in IR, the address information is sent from IR to AC.
After writing to/reading from Display Data RAM or Character
Generator RAM, AC is automatically incremented by one (or
decremented by one). The contents of AC are output to DB0 -
DB6 when RS = 0 and R/W = 1.
5.19. I/O Port Configuration
5.19.1. Input port: E
5.19.2. Input port: R / W, RS
5.19.3. Output port: CLK1, CLK2, M, D
5.19.4. Input / Output port: DB7 - 0
PMOS
NMOS
VDD
PMOS
NMOS
PMOS
VDD
VDD
PMOS
NMOS
VDD
PMOS
NMOS
VDD
PMOS
Data
Enable
VDD
VDD
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