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参数资料
| 型号： | SPLC783A |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16COM/80SEG Controller/Driver |
| 中文描述： | 16COM/80SEG控制器/驱动器 |
| 文件页数： | 9/38页 |
| 文件大小： | 2192K |
| 代理商： | SPLC783A |
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SPLC783A
5.3. Instruction Table
Sunplus Technology Co., Ltd.
Proprietary & Confidential
9
MAR. 10, 2005
Version: 1.4
Instruction Code
Execution time
Instruction
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Fosc=
190KHz
Fosc=
270KHz
Fosc=
350KHz
Clear Display
0
0
0
0
0
0
0
0
0
1
Write "20H" to DDRAM
and set DDRAM address
to "00H" from AC
2.16ms
1.52ms
1.18ms
Return Home
0
0
0
0
0
0
0
0
1
-
Set DDRAM address to
"00H"
from
AC
and
return
cursor
to
its
original position if shifted.
The contents of DDRAM
are not changed.
2.16ms
1.52ms
1.18ms
Entry Mode
Set
0
0
0
0
0
0
0
1
I/D
S
Assign cursor moving
direction and enable the
shift of entire display
53
s
38
s
29
s
Display ON/
OFF Control
0
0
0
0
0
0
1
D
C
B
Set
display
(D),
cursor(C), and blinking of
cursor(B) on/off control
bit.
53
s
38
s
29
s
Cursor or
Display Shift
0
0
0
0
0
1
S/C R/L
-
-
Set cursor moving and
display shift control bit,
and the direction, without
changing
of
DDRAM
data.
53
s
38
s
29
s
Function Set
0
0
0
0
1
DL
N
F
-
-
Set interface data length
(DL: 8-bit/4-bit), numbers
of
display
line
(N:
2-line/1-line) and, display
font
type
(F:5x10
dots/5x8 dots)
53
s
38
s
29
s
Set CGRAM
Address
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address in
address counter.
53
s
38
s
29
s
Set DDRAM
Address
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address in
address counter
53
s
38
s
29
s
Read Busy Flag
and Address
Counter
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
Whether during internal
operation or not can be
known by reading BF.
The contents of address
counter can also be
read.
Write Data to
RAM
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal
RAM (DDRAM/CGRAM).
53
s
38
s
29
s
Read Data from
RAM
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal
RAM (DDRAM/CGRAM).
53
s
38
s
29
s
Note:
"-": don't care
SunpusConidenia
Fo PARTMNERUseOny
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