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参数资料
| 型号： | SPLC783A |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16COM/80SEG Controller/Driver |
| 中文描述： | 16COM/80SEG控制器/驱动器 |
| 文件页数： | 27/38页 |
| 文件大小： | 2192K |
| 代理商： | SPLC783A |
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SPLC783A
6.5.3. Write mode (Writing Data from MPU to SPLC783A)
Sunplus Technology Co., Ltd.
Proprietary & Confidential
27
MAR. 10, 2005
Version: 1.4
Limit
Characteristics
Symbol
Min.
Typ.
Max.
Unit
Test Condition
E Cycle Time
t
C
500
-
-
ns
Pin E
E Pulse Width
t
PW
220
-
-
ns
Pin E
E Rise/Fall Time
t
R
, t
F
-
-
25
ns
Pin E
Address Setup Time
t
SP1
40
-
-
ns
Pins: RS, R/W, E
Address Hold Time
t
HD1
10
-
-
ns
Pins: RS, R/W, E
Data Setup Time
t
SP2
60
-
-
ns
Pins: DB0 - DB7
Data Hold Time
t
HD2
10
-
-
ns
Pins: DB0 - DB7
6.5.4. Read mode (Reading Data from SPLC783A to MPU)
Limit
Characteristics
Symbol
Min.
Typ.
Max.
Unit
Test Condition
E Cycle Time
t
C
500
-
-
ns
Pin E
E Pulse Width
t
W
220
-
-
ns
Pin E
E Rise/Fall Time
t
R
, t
F
-
-
25
ns
Pin E
Address Setup Time
t
SP1
40
-
-
ns
Pins: RS, R/W, E
Address Hold Time
t
HD1
10
-
-
ns
Pins: RS, R/W, E
Data Output Delay Time
t
D
-
-
120
ns
Pins: DB0 - DB7
Data hold time
t
HD2
20
-
-
ns
Pin DB0 - DB7
6.5.5. Interface mode with LCD Driver (SPLC100A1)
Limit
Characteristics
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Clock pulse width high
t
PWH
800
-
-
ns
Pins: CLK1, CLK2
Clock pulse width low
t
PWL
800
-
-
ns
Pins: CLK1, CLK2
Clock setup time
t
CSP
500
-
-
ns
Pins: CLK1, CLK2
Data setup time
t
DSP
300
-
-
ns
Pins: D
Data hold time
t
HD
300
-
-
ns
Pins: D
M delay time
t
D
-1000
-
1000
ns
Pins: M
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