参数资料
型号: SPT7936SCT
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: ADC
英文描述: 12-BIT, 28 MSPS SAMPLING A/D CONVERTER
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封装: TQFP-44
文件页数: 5/8页
文件大小: 59K
代理商: SPT7936SCT
5
8/1/00
SPT7936
Data
N-1
Data
N
Data
N+1
Data
Analog Input
Clock
N+2
tH
S
A
M
P
L
E
tAP
S
A
M
P
L
E
N
S
A
M
P
L
E
N+1
tD
GENERAL DESCRIPTION
The SPT7936 is a low power, 12-bit, 28 MSPS ADC. It has a
pipelined architecture and incorporates digital error correc-
tion of the 11 most significant bits. This error correction
ensures good linearity performance for input frequencies up
to Nyquist. The inputs are fully differential, making the device
insensitive to system-level noise. This device can also be
used in a single-ended mode. (See analog input section.)
With the power dissipation roughly proportional to the sam-
pling rate, this device is ideal for very low power applications
in the range of 1 to 28 MSPS.
TYPICAL INTERFACE CIRCUIT
The SPT7936 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7936 in
normal circuit operation. The following sections provide a descrip-
tion of the functions and outline critical performance criteria to
consider for achieving the optimal device performance.
Figure 1 - Timing Diagram
Figure 2 - Typical Interface Circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
VDD2
D9
G
G
G
G
G
G
O
G
G
D
D
VIN-
VIN+
GND
CM
Bias1
Bias0
GND
ExtRef
N/C
GND
Mini-Circuit
VIN
+3.3 V
+1.0 V
+2.0 V
1 k
1 k
1 k
+
+
4.7
μ
F
.01
μ
F
+
4.7
μ
F
.01
μ
F
+3.3 V
+3.3 V
.01
μ
F
(MSB)
(LSB)
Clock Input
+3.3 V
FB
(*)
Bias1
Bias0
ExtRef
50
68 pF
.01
μ
F
SPT7936
VD1
VD1
VD1
VD
VD2
VD2
G
VR
VR
C
G
NOTES:
1) Place the ferrite bead (*) as close to the device as possible.
2) Place 0.01 microfarad capacitors as close to the device as possible.
3) All capacitors are surface-mount unless otherwise specified.
4) All input pins (references, analog input, clock input) must be
protected. (See absolute maximum rating.)
5) Set Bias1 and Bias0 for maximum sample rate.
Bias1Bias0
0
0
Sleep mode
0
1
Max. 5 MHz sampling
1
0
Max. 20 MHz sampling
1
1
Max. 28 MHz sampling
6) Use internal or external reference. Do not connect external voltage reference when using internal references.
7) All VDD1 and VDD2 must be connected together. Do not leave any pin unconnected.
I
4.7
μ
F
.01
μ
F
.01
μ
F
BGAP
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