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| 型号： | SSL1750T/N1,518 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 11/29页 |
| 文件大小： | 0K |
| 描述： | IC LED DRVR HI PWR AC IN 16-SOIC |
| 标准包装： | 2,500 |
| 拓扑： | 交直流离线开关，反激式，PFC |
| 输出数： | 2 |
| 内部驱动器： | 无 |
| 类型 - 主要： | 通用 |
| 频率： | 100kHz ~ 150kHz |
| 电源电压： | 70 V ~ 276 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SO |
| 包装： | 带卷 (TR) |
| 工作温度： | -20°C ~ 150°C |
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NXP Semiconductors
S1
SSL1750
SMPS control IC for LED drivers
Istart(soft)PFC ≤ 60 μ A
SOFT START
SOFT STOP
CONTROL
RSS1
CSS1
11
PFCSENSE
+
0.5 V
OCP
RSENSE1
014aaa018
Fig 6.
Soft start-up and soft-stop of PFC
7.2.6 Burst mode control
When the output power of the ?yback converter (see Section 7.3 ) is low, the ?yback
converter switches over to frequency reduction mode. When frequency reduction mode is
entered by the ?yback controller, the power factor correction circuit switches to burst mode
control.
In burst mode control, switching of the power factor correction circuit is inhibited until the
voltage on pin VOSENSE has dropped to V burst(L) . Switching then restarts with a soft-start
to avoid audible noise (see Section 7.2.5 ). As soon as the voltage on pin VOSENSE
reaches V burst(H) the soft-stop circuit is activated, again to avoid audible noise. During the
soft-stop time the output voltage of the power factor correction circuit overshoots,
depending on the soft-start resistor and capacitor, R SS1 and C SS1 on pin PFCSENSE. As
the V burst(H) voltage is well below the V reg(VOSENSE) voltage, the PFC output voltage does
not reach the normal operation output voltage of the power factor correction circuit in a
typical application due to this overshoot.
The burst mode repetition rate is de?ned by the output power and the value of the bus
capacitor, C bus .
During burst mode operation pin PFCCOMP is clamped between a voltage of 2.7 V (typ)
and 3.9 V (typ). The lower clamp voltage limits the maximum power that is delivered
during burst mode operation and yields a more sinusoidal input current during the burst
pulse. The upper clamp voltage ensures that the PFC can return to its normal regulation
point in a limited amount of time when returning from burst mode.
As soon as the ?yback converter leaves frequency reduction mode, the power factor
correction circuit restores normal operation. To prevent continuous on and off switching of
the PFC circuit, a small hysteresis has been built in (50 mV (typ) on pin FBCTRL).
SSL1750_1
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 15 September 2008
11 of 29
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