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| 型号： | SSL1750T/N1,518 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 6/29页 |
| 文件大小： | 0K |
| 描述： | IC LED DRVR HI PWR AC IN 16-SOIC |
| 标准包装： | 2,500 |
| 拓扑： | 交直流离线开关，反激式，PFC |
| 输出数： | 2 |
| 内部驱动器： | 无 |
| 类型 - 主要： | 通用 |
| 频率： | 100kHz ~ 150kHz |
| 电源电压： | 70 V ~ 276 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SO |
| 包装： | 带卷 (TR) |
| 工作温度： | -20°C ~ 150°C |
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NXP Semiconductors
SSL1750
SMPS control IC for LED drivers
12
8
11
9
16 13
10
6
SSL1750T
7
4
Fig 4.
3
Typical con?guration of SSL1750
2
1
014aaa350
7.1.1 Start-up and undervoltage lockout
Initially the capacitor on pin V CC is charged from the high voltage mains via pin HV.
As long as V CC is below V trip , the charge current is low. This protects the IC in case pin
V CC is shorted to ground. For a short start-up time the charge current above V trip is
increased until V CC reaches V th(UVLO) . If V CC is between V th(UVLO) and V startup , the charge
current is low again, ensuring a low duty cycle during fault conditions.
The control logic activates the internal circuitry and switches off the charge current when
the voltage on pin V CC passes the V startup level. First, the output on pin LATCH is activated
and the soft-start capacitors on the pins PFCSENSE and FBSENSE are charged. When
the voltage on pin LATCH exceeds the V en(LATCH) voltage and the soft-start capacitor on
pin PFCSENSE is charged, the PFC circuit is activated. The supply current from the pin
HV is then switched on again and the PFC circuit charges the C bus capacitor. When the
voltage on pin VOSENSE reaches the V start(fb) level, the charge current is switched off and
the ?yback converter is activated (providing the soft-start capacitor on pin FBSENSE is
charged). The output voltage of the ?yback converter is then regulated to its nominal
output voltage. The IC supply is taken over by the auxiliary winding of the ?yback
converter. See Figure 5 .
When the PFC is started, there is initially no supply takeover from the auxiliary winding. To
make a small V CC capacitor possible, the V CC voltage is regulated to the V startup level, as
long as the ?yback converter has not yet started. Regulation is done by hysteretic control
with a limited (high level) charge current. The hysteresis is typically 300 mV.
If during start-up pin LATCH does not reach the V en(LATCH) level before V CC reaches
V th(UVLO) , its output is deactivated and the charge current is switched on again.
SSL1750_1
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 15 September 2008
6 of 29
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