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参数资料
| 型号： | SSP-21116-010-B |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, DMA16 |
| 封装： | DIP-16 |
| 文件页数： | 7/12页 |
| 文件大小： | 185K |
| 代理商： | SSP-21116-010-B |
4
Data Device Corporation
www.ddc-web.com
SSP-21116
J-03/03-0
FUNCTIONAL DESCRIPTION
The SSP-21116 series of Solid-State Power Controllers incorpo-
rate the wire protection feature of electromechanical circuit
breakers and the reliability of solid-state relays. In addition to the
solid-state relay's input logic compatibility, the SSP-21116 series
provides logic compatible status outputs.
A TTL/CMOS compatible input provides external control of the
power switch's “ON/OFF” state. A logic high on this control input
turns the power to the load “on”. A logic low will turn the power
switch off, which removes power from the load.
In the event of an overload, the SSP-21116 series will trip, just
like a circuit breaker, and automatically remove power from the
load. In order to turn back on, the control input must be brought
to a logic low, and then returned to a logic high state.
As in a circuit breaker, the SSPC's time to trip depends on the
current level. Slight overloads will cause longer trip times. Heavy
overloads will cause shorter trip times. The fault ("Instant Trip")
and I
2T trip curve, FIGURE 2, shows the trip time as a function
of current for a single trip or repetitive trips with at least 10 sec-
onds between trip and turn on. Attempts to repeatedly turn on
into an overload will result in the thermal memory shortening
each trip time. This "memory" protects the wire, load and Solid-
State Power Controller.
The status lines are TTL/CMOS compatible outputs which reflect
the state of the SSPC, the load and the Built-In-Test (BIT) cir-
cuits. The status permits an external subsystem to monitor and
ultimately control the SSPC. TABLE 5 defines the status lines'
states which indicate the various states of the SSPC. Further
explanation of the status lines appears in the applications infor-
mation section.
The SSP-21116 series SSPC's are characterized by their current
rating and maximum "on" resistance listed in TABLE 4. These
parameters are established by the number of Power FET's
placed in parallel within the SSPC.
The trip function is implemented by two separate circuits, a true
I
2T trip comparator and a short circuit fault comparator. They are
independent of each other but work together to protect the sys-
tem.
If the load current is less than 110% of rated current, the SSPC
will never trip. If the load current is greater than 145%, the SSPC
will always trip.
For load currents less than 800%, the trip time can be found from
FIGURE 2 by drawing a horizontal line on FIGURE 2 at the cur-
rent level of interest. The SSPC will always trip at a time between
the two curves. This is true I
2T tripping.
When the SSPC trips in accordance with the I
2T characteristics,
the fall time is 200 s, maximum.
For load currents greater than 1200%, the SSPC will turn off in
less than 25
s. Between 800% and 1200%, the SSPC will turn
off in a time less than the "max. trip limit" shown in FIGURE 2
and may turn off in less than 25
s. When the SSPC turns off
under these fault conditions, the fall time is less than 25
s.
10,000
1,200
1,000
800
600
400
200
0
10
1.0
0.1
0.01
0.001
s
25
145%
.
TIME - SECONDS
LOAD
CURRENT
%
I
-
MAX
NEVER TRIP
MIN. TRIP LIMIT
INSTANT
TRIP
ALWAYS TRIP
MAX. TRIP LIMIT
15 AMP I T
10 AMP AND BELOW I T
2
110%
FIGURE 2. TRIP CHARACTERISTICS
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