参数资料
型号: SST25VF020B-80-4I-QAE
厂商: Microchip Technology
文件页数: 19/35页
文件大小: 0K
描述: IC FLASH SER 2MB 80MHZ SPI 8WSON
标准包装: 98
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 2M (256K x 8)
速度: 80MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-WDFN 裸露焊盘
供应商设备封装: 8-WSON
包装: 管件
2 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF020B
Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven
high before the instruction is executed. The user may poll the Busy bit in the software status register or wait
T CE for the completion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase
sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7
SCK
SI
SO
MODE 0
60 or C7
MSB
HIGH IMPEDANCE
1417 ChEr.0
Figure 15: Chip-Erase Sequence
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The Status Regis-
ter may be read at any time even during a Write (Program/Erase) operation. When a Write operation is
in progress, the Busy bit may be checked before sending any new commands to assure that the new
commands are properly received by the device. CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing
clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR
instruction sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
MODE 0
SI
MSB
05
SO
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
1417 RDSRseq.0
Figure 16: Read-Status-Register (RDSR) Sequence
?2012 Silicon Storage Technology, Inc.
19
DS25054A
01/12
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