参数资料
型号: SST25VF080B-80-4C-QAE-T
厂商: Microchip Technology
文件页数: 9/37页
文件大小: 0K
描述: IC FLASH SER 8MB 50MHZ SPI 8WSON
标准包装: 2,000
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 8M(1M x 8)
速度: 80MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 8-WDFN 裸露焊盘
供应商设备封装: 8-WSON
包装: 带卷 (TR)
8 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF080B
Data Sheet
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25VF080B. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-
Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed
first. The complete list of instructions is provided in Table 5. All instructions are synchronized off a high
to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signif-
icant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Address
Dummy
Data
Instruction
Description
Op Code Cycle 1
Cycle(s) 2 Cycle(s) Cycle(s)
Read
High-Speed Read
Read Memory
Read Memory at higher
0000 0011b (03H)
0000 1011b (0BH)
3
3
0
1
1 to ?
1 to ?
speed
4 KByte Sector-Erase 3 Erase 4 KByte of
0010 0000b (20H)
3
0
0
memory array
32 KByte Block-Erase 4 Erase 32 KByte block
0101 0010b (52H)
3
0
0
of memory array
64 KByte Block-Erase 5 Erase 64 KByte block
1101 1000b (D8H)
3
0
0
of memory array
Chip-Erase
Erase Full Memory Array
0110 0000b (60H) or
0
0
0
1100 0111b (C7H)
Byte-Program
AAI-Word-Program 6
To Program One Data Byte
Auto Address Increment
0000 0010b (02H)
1010 1101b (ADH)
3
3
0
0
1
2 to ?
Programming
RDSR 7
Read-Status-Register
0000 0101b (05H)
0
0
1 to ?
EWSR
Enable-Write-Status-Register 0101b 0000b (50H)
0
0
0
WRSR
WREN
WRDI
RDID 8
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H) or
0
0
0
3
0
0
0
0
1
0
0
1 to ?
1010 1011b (ABH)
JEDEC-ID
EBSY
JEDEC ID read
Enable SO to output RY/BY#
1001 1111b (9FH)
0111 0000b (70H)
0
0
0
0
3 to ?
0
status during AAI programming
DBSY
Disable SO as RY/BY#
1000 0000b (80H)
0
0
0
status during AAI programming
T5.0
25045
1.
2.
3.
4.
5.
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be V IL or V IH .
4KByte Sector Erase addresses: use A MS -A 12, remaining addresses are don’t care but must be set either at V IL or V IH.
32KByte Block Erase addresses: use A MS -A 15, remaining addresses are don’t care but must be set either at V IL or V IH.
64KByte Block Erase addresses: use A MS -A 16, remaining addresses are don’t care but must be set either at V IL or V IH.
?2011 Silicon Storage Technology, Inc.
9
DS25045A
09/11
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