参数资料
型号: SST25WF080-75-4I-SAF-T
厂商: Microchip Technology
文件页数: 11/33页
文件大小: 0K
描述: I CFLASH SER 8MN 75MHZ SPI 8SOIC
标准包装: 3,300
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 8M(1M x 8)
速度: 75MHz
接口: SPI 串行
电源电压: 1.65 V ~ 1.95 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
8 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF080
Not Recommended for New Designs
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25WF080. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-
Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment (AAI)
programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The com-
plete instructions are provided in Table 6. All instructions are synchronized off a high-to-low transition
of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE#
must be driven low before an instruction is entered and must be driven high after the last bit of the
instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any
low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the
instruction in progress and return the device to standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most significant bit (MSB) first.
Table 6: Device Operation Instructions for SST25WF080
Address
Dummy
Data
Maximum
Instruction
Description
Op Code Cycle 1
Cycle(s) 2 Cycle(s) Cycle(s) Frequency
Read
High-Speed
Read Memory
Read Memory at Higher Speed
0000 0011b (03H)
0000 1011b (0BH)
3
3
0
1
1 to ?
1 to ?
33 MHz
Read
4 KByte Sec- Erase 4 KByte of memory array
0010 0000b (20H)
3
0
0
tor-Erase 3
32 KByte
Erase 32 KByte block
0101 0010b (52H)
3
0
0
Block-Erase 4
of memory array
64 KByte
Erase 64 KByte block
1101 1000b (D8H)
3
0
0
Block-Erase 5
of memory array
Chip-Erase
Erase Full Memory Array
0110 0000b (60H) or
0
0
0
1100 0111b (C7H)
Byte-Program To Program One Data Byte
0000 0010b (02H)
3
0
1
AAI-Word-
Program 6
RDSR 7
EWSR 8
WRSR
WREN 8
WRDI
RDID 9
Auto Address Increment
Programming
Read-Status-Register
Enable-Write-Status-Register
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
1010 1101b (ADH)
0000 0101b (05H)
0110 0000b (50H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H) or
3
0
0
0
0
0
3
0
0
0
0
0
0
0
2 to ?
1 to ?
0
1
0
0
1 to ?
75 MHz
1010 1011b (ABH)
EBSY
Enable SO to output RY/BY#
0111 0000b (70H)
0
0
0
status during AAI programming
DBSY
Disable SO to output RY/BY#
1000 0000b (80H)
0
0
0
status during AAI programming
JEDEC-ID
EHLD
JEDEC ID read
Enable HOLD# pin functionality
1001 1111b (9FH)
1010 1010b (AAH)
0
0
0
0
3 to ?
0
of the RST#/HOLD# pin
T6.0 25024
1.
2.
3.
4.
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be V IL or V IH .
4 KByte Sector-Erase addresses: use A MS -A 12, remaining addresses are don’t care but must be set either at V IL or V IH.
32 KByte Block-Erase addresses: use A MS -A 15, remaining addresses are don’t care but must be set either at V IL or V IH.
?2012 Silicon Storage Technology, Inc.
11
DS25024B
03/12
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