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| 型号： | SST39VF1602C-70-4C-EKE |
| 厂商： | Microchip Technology |
| 文件页数： | 4/33页 |
| 文件大小： | 0K |
| 描述： | IC FLASH MPF 16MBIT 70NS 48TSOP |
| 标准包装： | 96 |
| 系列： | SST39 MPF™ |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 16M (1M x 16) |
| 速度： | 70ns |
| 接口： | 并联 |
| 电源电压： | 2.7 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 48-TFSOP（0.724"，18.40mm 宽） |
| 供应商设备封装： | 48-TSOP |
| 包装： | 托盘 |
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16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ 6 will produce alternating ‘1’s
and ‘0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ 6 bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ 6 )
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ 6 will be set to ‘1’ if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ 6 will toggle.
An additional Toggle Bit is available on DQ 2 , which can be
used in conjunction with DQ 6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ 2 ) is valid after the rising edge of the last WE# (or CE#)
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST39VF1602C supports top hardware block protec-
tion, which protects the top 8 KWord block of the device.
The SST39VF1601C supports bottom hardware block pro-
tection, which protects the bottom 8KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 8 KWord when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
TABLE 2: Boot Block Address Ranges
pulse of Write operation. See Figure 10 for Toggle Bit tim-
ing diagram and Figure 23 for a flowchart.
Product
Bottom Boot Block
Address Range
TABLE 1: Write Operation Status
Status DQ 7 DQ 6
Normal Standard DQ 7 # Toggle
Operation Program
DQ 2
No
Toggle
RY/BY#
0
SST39VF1601C
Top Boot Block
SST39VF1602C
00000H - 01FFFH
FE000H - FFFFFH
T2.0 1380
Standard
Erase
0
Toggle
Toggle
0
Hardware Reset (RST#)
Erase-
Suspend
Mode
Read from
Erase-
Suspended
Sector/
Block
Read from
Non-Erase-
Suspended
1
Data
1
Data
Toggle
Data
1
1
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T RP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T RHR is
required after RST# is driven high before a valid Read can
take place (see Figure 18).
Sector/Block
Program DQ 7 # Toggle N/A
Note: DQ 7 and DQ 2 require a valid address when reading
status information.
0
T1.0 1380
The Erase or Program operation that has been interrupted
needs to be re-initiated after the device resumes normal
operation mode to ensure data integrity.
Data Protection
The SST39VF1601C/1602C provide both hardware and
software features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V DD Power Up/Down Detection: The Write operation is
inhibited when V DD is less than 1.5V.
Software Data Protection (SDP)
The SST39VF1601C/1602C provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
7 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
?2010 Silicon Storage Technology, Inc.
4
S71380-04-000
05/10
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| SST39VF1602C-70-4C-MAQE | 功能描述:闪存 2.7V to 3.6V 16Mbit Multi-Purpose 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39VF1602C-70-4I-B3KE | 功能描述:闪存 16M (1Mx16) 70ns Industrial Temp RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39VF1602C-70-4I-B3KE-T | 功能描述:闪存 2.7 to 3.6V 16Mbit Multi-Purpose 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39VF1602C-70-4I-EKE | 功能描述:闪存 16M (1Mx16) 70ns Industrial Temp RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39VF1602C-70-4I-MAQE | 功能描述:闪存 2.7V to 3.6V 16Mbit Multi-Purpose 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
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