- 您现在的位置：买卖IC网 > PDF目录4545 > SST39VF400A-70-4I-MAQE (Microchip Technology)IC FLASH MPF 4MBIT 70NS 48-WFBGA PDF资料下载
参数资料
| 型号： | SST39VF400A-70-4I-MAQE |
| 厂商： | Microchip Technology |
| 文件页数： | 8/37页 |
| 文件大小： | 0K |
| 描述： | IC FLASH MPF 4MBIT 70NS 48-WFBGA |
| 特色产品： | SST Serial and Parallel Flash Memory |
| 标准包装： | 740 |
| 系列： | SST39 MPF™ |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 4M (256K x 16) |
| 速度： | 70ns |
| 接口： | 并联 |
| 电源电压： | 2.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-WFBGA |
| 供应商设备封装： | 48-WFBGA（6x4） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
A Microchip Technology Company
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the ris-
ing edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid
read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing dia-
gram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored.
Write Operation Status Detection
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide two software means to detect
the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time.
The software detection includes two status bits: Data# Polling (DQ 7 ) and Toggle Bit (DQ 6 ). The End-of-
Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ 7 or DQ 6 . In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the write cycle, otherwise the rejection is valid.
Data# Polling (DQ 7 )
When the SST39LF200A/400A/800A and SST39VF200A/400A/800A are in the internal Program oper-
ation, any attempt to read DQ 7 will produce the complement of the true data. Once the Program oper-
ation is completed, DQ 7 will produce true data. Note that even though DQ 7 may have valid data
immediately following the completion of an internal Write operation, the remaining data outputs may
still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after
an interval of 1 μs . During internal Erase operation, any attempt to read DQ 7 will produce a ‘0’. Once
the internal Erase operation is completed, DQ 7 will produce a ‘1’. The Data# Polling is valid after the
rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling
timing diagram and Figure 19 for a flowchart.
Toggle Bit (DQ 6 )
During the internal Program or Erase operation, any consecutive attempts to read DQ 6 will produce
alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is
completed, the DQ 6 bit will stop toggling. The device is then ready for the next operation. The Toggle
Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-
or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for
Toggle Bit timing diagram and Figure 19 for a flowchart.
Data Protection
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
? 2011 Silicon Storage Technology, Inc.
8
DS25001A
03/11
相关PDF资料 |
PDF描述 |
|---|---|
| SST39VF1602-70-4I-EKE | IC FLASH MPF 16MBIT 70NS 48TSOP |
| 25LC256-I/MF | IC EEPROM 256KBIT 10MHZ 8DFN |
| 24FC512-I/ST | IC EEPROM 512KBIT 1MHZ 8TSSOP |
| 25LC512-I/MF | IC EEPROM 512KBIT 20MHZ 8DFN |
| SST39VF1601-70-4I-EKE | IC FLASH MPF 16MBIT 70NS 48TSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SST39VF400A-70-4I-MAQE-T | 功能描述:闪存 2.7V to 3.6V 4Mbit Multi-Prps Fl RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39VF400A-90-4C-B3K | 功能描述:闪存 R 804-39VF400A7CB3KE RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39VF400A-90-4C-EK | 功能描述:闪存 R 804-39VF400A7CEKE RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39VF401C-70-4C-B3KE | 功能描述:闪存 2.7V to 3.6V 4Mbit Multi-Purpose 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39VF401C-70-4C-B3KE-T | 功能描述:闪存 2.7V to 3.6V 4Mbit Multi-Purpose 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。