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参数资料
| 型号： | SST39WF800B-70-4I-MAQE |
| 厂商： | Microchip Technology |
| 文件页数： | 7/33页 |
| 文件大小： | 0K |
| 描述： | IC FLASH MPF 8MBIT 70NS 48WFBGA |
| 特色产品： | SST Serial and Parallel Flash Memory |
| 标准包装： | 740 |
| 系列： | SST39 MPF™ |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 8M（512K x 16） |
| 速度： | 70ns |
| 接口： | 并联 |
| 电源电压： | 1.65 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-WFBGA |
| 供应商设备封装： | 48-WFBGA（6x4） |
| 包装： | 托盘 |
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8 Mbit (x16) Multi-Purpose Flash
A Microchip Technology Company
SST39WF800B
Data Sheet
Sector-/Block-Erase Operation
The SST39WF800B offers both Sector-Erase and Block-Erase modes which allow the system to erase
the device on a sector-by-sector, or block-by-block, basis.
The sector architecture is based on uniform sector size of 2 KWord. Initiate the Sector-Erase operation
by executing a six-byte command sequence with Sector-Erase command (30H) and sector address
(SA) in the last bus cycle.
The Block-Erase mode is based on uniform block size of 32 KWord. Initiate the Block-Erase operation
by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA)
in the last bus cycle.
The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command
(30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins
after the sixth WE# pulse.
The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See
Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase
operation are ignored.
Chip-Erase Operation
The SST39WF800B provides a Chip-Erase operation, which allows the user to erase the entire mem-
ory array to the ‘1’ state. This is useful when the entire device must be quickly erased.
Initiate the Chip-Erase operation by executing a six-byte command sequence with Chip-Erase com-
mand (10H) at address 5555H in the last byte sequence.
The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. Dur-
ing the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 9 for the timing diagram, and Figure 20 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Write Operation Status Detection
To optimize the system write cycle time, the SST39WF800B provides two software means to detect the
completion of a Program or Erase write cycle. The software detection includes two status bits—Data#
Polling (DQ 7 ) and Toggle Bit (DQ 6 ). The End-of-Write detection mode is enabled after the rising edge
of WE#, which initiates the internal Program or Erase operation.
The completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may occur simultaneously with the completion of the Write cycle. If this
occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ 7
or DQ 6 . To prevent spurious rejection in the event of an erroneous result, the software routine must
include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then
the device has completed the Write cycle, otherwise the rejection is valid.
?2011 Silicon Storage Technology, Inc.
7
DS25031A
08/11
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