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参数资料
| 型号： | SST39WF800B-70-4I-MAQE |
| 厂商： | Microchip Technology |
| 文件页数： | 8/33页 |
| 文件大小： | 0K |
| 描述： | IC FLASH MPF 8MBIT 70NS 48WFBGA |
| 特色产品： | SST Serial and Parallel Flash Memory |
| 标准包装： | 740 |
| 系列： | SST39 MPF™ |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 8M（512K x 16） |
| 速度： | 70ns |
| 接口： | 并联 |
| 电源电压： | 1.65 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-WFBGA |
| 供应商设备封装： | 48-WFBGA（6x4） |
| 包装： | 托盘 |
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8 Mbit (x16) Multi-Purpose Flash
A Microchip Technology Company
SST39WF800B
Data Sheet
Data# Polling (DQ 7 )
When the SST39WF800B is in the internal Program operation, any attempt to read DQ 7 will produce
the complement of the true data. Once the Program operation is complete, DQ 7 will produce true data.
Although DQ 7 may have valid data immediately following the completion of an internal Write operation,
the remaining data outputs may still be invalid. Valid data on the entire data bus will appear in subse-
quent successive Read cycles after an interval of 1 μs . During an internal Erase operation, any attempt
to read DQ 7 will produce a ‘0’. Once the internal Erase operation is complete, DQ 7 will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 8 for Data# Polling timing diagram and Figure 18 for a flowchart.
Toggle Bit (DQ 6 )
During the internal Program or Erase operation, any consecutive attempts to read DQ 6 will produce
alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’.
When the Program or Erase operation is complete, the DQ 6 bit will stop toggling and the device is
ready for the next operation.
The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse.
See Figure 0-1 for Toggle Bit timing diagram and Figure 18 for a flowchart.
Data Protection
The SST39WF800B provides both hardware and software features to protect nonvolatile data from
inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection : A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
V DD Power Up/Down Detection: The Write operation is inhibited when V DD is less than 1.0V.
Write Inhibit Mode : Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39WF800B provides the JEDEC approved Software Data Protection scheme for all data alter-
ation operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-
byte sequence. The three-byte load sequence is used to initiate the Program operation, providing opti-
mal protection from inadvertent Write operations, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped
with the Software Data Protection permanently enabled. See Table 4 for the specific software com-
mand codes. During SDP command sequence, invalid commands will abort the device to Read mode
within T RC . The contents of DQ 15 -DQ 8 can be V IL or V IH , but no other value, during any SDP command
sequence.
?2011 Silicon Storage Technology, Inc.
8
DS25031A
08/11
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