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参数资料
| 型号： | SST55LC100-45-C-TQWE |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PQFP100 |
| 封装： | ROHS COMPLIANT, MS-026AED, TQFP-100 |
| 文件页数： | 20/80页 |
| 文件大小： | 758K |
| 代理商： | SST55LC100-45-C-TQWE |
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Advance Information
CompactFlash Card Controller
SST55LC100
2005 Silicon Storage Technology, Inc.
S71298-00-000
10/05
27
9.1.4 True IDE Mode Addressing
When the CompactFlash card is configured in the True IDE mode, the I/O decoding is as follows:
9.1.5 CF-ATA Registers
The following section describes the hardware registers used by the host software to issue commands to the Com-
pactFlash device. These registers are often collectively referred to as the “task file.”
Note: In accordance with the PCMCIA specification: each of the registers below which is located at an odd offset
address may be accessed at its normal address and also the corresponding even address (normal address
-1) using data bus lines (D15-D8) when CE1# is high and CE2# is low unless IOIS16# is high (not asserted)
and an I/O cycle is being performed.
9.1.5.1 Data Register (Address - 1F0H[170H];Offset 0,8,9)
The Data register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash card data
buffer and the Host. This register overlaps the Error register. The table below describes the combinations of data
register access and is provided to assist in understanding the overlapped Data register and Error/Feature register
rather than to attempt to define general PCMCIA word and byte access modes and operations. See the PCMCIA
PC Card Standard Release 2.0 for definitions of the Card Accessing Modes for I/O and Memory cycles.
Note: Because of the overlapped registers, access to the 1F1H, 171H or offset 1 are not defined for word (CE2#=0
and CE1#=0) operations. These accesses are treated as accesses to the Word Data register. The dupli-
cated registers at offsets 8, 9 and DH have no restrictions on the operations that can be performed by the
socket.
TABLE
9-5: TRUE IDE MODE I/O DECODING
CE2#
CE1#
A2
A1
A0
IORD#=0
IOWR#=0
1
0
RD Data
WR Data
1
0
1
Error register
Features
1
0
1
0
Sector Count
1
0
1
Sector No.
1
0
1
0
Cylinder Low
1
0
1
0
1
Cylinder High
1
0
1
0
Select Card/Head
1
0
1
Status
Command
0
1
0
Alt Status
Device Control
T9-5.0 1298
Data Register
CE2#
CE1#
A0
Offset
Data Bus
Word Data Register
0
X
0,8,9
D15-D0
Even Data Register
1
0
0,8
D7-D0
Odd Data Register
1
0
1
9
D7-D0
Odd Data Register
0
1
X
8,9
D15-D8
Error / Feature Register
1
0
1
1, DH
D7-D0
Error / Feature Register
0
1
X
1
D15-D8
Error / Feature Register
0
X
DH
D15-D8
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SST55LC100-45-I-BWE | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:CompactFlash Card Controller |
| SST55LC100-45-I-TQWE | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:CompactFlash Card Controller |
| SST55LC100M | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:CompactFlash Card Controller |
| SST55LC100M-45-C-BWE | 功能描述:总线收发器 Compact Flash 45MHz 3.3V Commercial RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| SST55LC100M-45-C-TQWE | 功能描述:总线收发器 Compact Flash 45MHz 3.3V Commercial RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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