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参数资料
| 型号： | SST89C58RC-40-I-TQJE |
| 厂商： | Microchip Technology |
| 文件页数： | 44/88页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT FLASH 40TQFP |
| 标准包装： | 160 |
| 系列： | FlashFlex® |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | EBI/EMI，I²C，SMBus，UART/USART |
| 外围设备： | 欠压检测/复位，POR，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-TQFP |
| 包装： | 托盘 |
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2011 Silicon Storage Technology, Inc.
DS25100A
12/11
49
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
Figure 21:Data Transfer on the SUBus
SDA (Serial Data Line)
The SDA line is the SMBus serial data line, and is primarily driven by the master or slave transmitter.
The SDA is changeable when SCL is low, and SDA is stable when SCL is high. Perform bus arbitration
on SDA when SCL is high.
SCL (Serial Clock Line)
The SCL line is the SMBus serial clock line which provides synchronized transmissions between mas-
ter and slave devices and is driven by the master devices. When multiple masters drive the SCL simul-
taneously, a wired-AND combines all signals into one synchronized clock signal. The slowest clock
determines the synchronized LOW period and the fastest clock determines the HIGH period.
SMBus Modes of Operation
The SMBus transaction begins with a START which is followed by an address byte and data, and then
ends with a STOP. An acknowledge bit from the receiver follows the address byte, which consists of a
7-bit address plus a direction bit, and each data byte. The direction bit (R/W), which occupies the least
significant bit position of the address, indicates a READ operation when set to logic ‘1’, and a WRITE
operation when set to logic ‘0’. The master can address multiple slaves simultaneously using a general
call address (0x00 + R/W), which is recognized by all slave devices.
The master initiates all transactions with one or more target-addressed slave devices. After generating
a START condition, the master transmits the address and direction bit. For a master-to-slave WRITE
operation, data is transmitted a byte at a time from the master; waiting for an acknowledge after each
byte from the slave. For a slave-to-master READ operation, the slave awaits an acknowledge after
each byte from the master. The master generates a STOP which ends the transaction and frees the
bus at the completion of the data transfer.
At any time, the SMBus is configured to operate in either master or slave mode.
Master Transmitter Mode
The serial data is output through SDA while SCL supplies the serial clock. The first transmitted byte
contains the slave address and the data direction bit. In this WRITE operation mode, the data direction
bit (R/W) will be logic ‘0’ and the master transmits serial data. After each byte is transmitted, an
acknowledge bit is received from the slave. START and STOP conditions are output by the master to
indicate the beginning and the end of a serial transfer.
Start
Condition
SDA
Stop
Condition
1323 F45.0
SCL
9
3-8
2
1
2
19
8
7
P/S
Repeated
Start
Condition
ACK
from
REC
ACK
from
REC
MSB
Slave Address
S
R/W
Direction
Bit
Repeated if more bytes are transferred
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