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| 型号： | SST89C58RC-40-I-TQJE |
| 厂商： | Microchip Technology |
| 文件页数： | 47/88页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT FLASH 40TQFP |
| 标准包装： | 160 |
| 系列： | FlashFlex® |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | EBI/EMI，I²C，SMBus，UART/USART |
| 外围设备： | 欠压检测/复位，POR，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-TQFP |
| 包装： | 托盘 |
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2011 Silicon Storage Technology, Inc.
DS25100A
12/11
51
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
SMBus SFR
The SST89C58RC has two identical SMBus interfaces, each identical with the exception of the SFR
addresses and the I/O pins associated with each interface.
The SMBus interfaces operate as a master and/or slave and can function on a bus with multiple mas-
ters. The SMBus controls the SDA, the generation and synchronization of the SCL, the arbitration
logic, and the control and generation of START/STOP. The following SFRs are associated with the
SMBus.
SMBus Control Register
SMBus control register SM0CON0 configures and controls the SMBus interface making all bits in the
register software readable and writable. The SMBus hardware sets the Serial Interrupt flag (SI_0,
SMCON0.4) to logic ‘1’ when a valid serial interrupt condition occurs; and clears the Stop flag (STO_5,
SM0CON0.4) to logic ‘0’ when a STOP condition is present on the bus.
Enable the SMBus interface, by setting the SMBEN_0 flag to logic ‘1’; disable and remove it from the
bus by clearing the ENSMB flag to logic ‘0’. To reset the SMBus communication, momentarily clear the
SMBEN flag and then reset it to logic ‘1’. Using SMBEN to temporarily remove a device from the bus
will result in lost information. The best method to temporarily remove a device from the bus is to use
the Assert Acknowledge (AA) flag.
If the bus is idle, SMBus generates a START condition after a delay of 1.5 baud rate clock cycle when
the Start flag (STA_0, Sm0CON0.6) is set. If STA and STADY bits are both set in the first transmission
(that is, the SMBEN is set from “0” to “1”) and bus is idle, a START condition will be generated after 10
baud rate clock cycles. If SMBUS is already in the master mode and one or more than one bytes has
been transmitted or received, a repeated START condition will be generated when STA bit is set. If
SMBus is in addressed slave mode and the STA is set, no START condition will be generated until
SMBus enters “not addressed slave” mode and the bus is idle. STA bit only can be cleared by software.
In master mode, a STOP condition is transmitted on the bus when the Stop flag (STO_0, SM0CON0.5)
is set. And STO bit is cleared by hardware automatically after a STOP condition is detected on the bus.
If STA and STO bits are both set, the STOP condition is transmitted firstly, and then the START condi-
tion is transmitted.
Table 18:SMBus SFR Functions
SFR
Function
SM0CON0 / SM0CON1
Configures SMBus0
SM0STA
Controls status of SMBus0
SM0DAT
Data register for transmitting and receiving SMBus0 data
SM0ADR
Indicates SMBus0 slave address
SM0SCLH / SM0SCLL
Configures SMBus0 High/Low duty
SM1CON0 / SM1CON1
Configures SMBus1
SM1STA
Controls status of SMBus1
SM1DAT
Data register for transmitting and receiving SMBus1 data
SM1ADR
Indicates SMBus1 slave address
SM1SCLH / SM1SCLL
Configures SMBus1 High/Low duty
T0-0.25100
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