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参数资料
| 型号： | SST89C58RC-40-I-TQJE |
| 厂商： | Microchip Technology |
| 文件页数： | 49/88页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT FLASH 40TQFP |
| 标准包装： | 160 |
| 系列： | FlashFlex® |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | EBI/EMI，I²C，SMBus，UART/USART |
| 外围设备： | 欠压检测/复位，POR，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-TQFP |
| 包装： | 托盘 |
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2011 Silicon Storage Technology, Inc.
DS25100A
12/11
53
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
Data Register
The SMBus Data register (SM0DAT0) holds a byte of recently received or ready-to-transmit serial data.
When SI is set to logic ‘1’, the data in the register is stable. In this state, software safely reads or writes the
data register. However, when the SMBus is enabled and the SI flag is cleared to logic ‘0’, the software must
not access the SM0DAT register because the hardware may be shifting a data byte in or out of the register.
After the SM0DAT receives a byte of data, the first bit of the serial data byte is located at the MSB. As data
is shifted out of the SM0DAT, beginning with the MSB, data from the bus is simultaneously shifted in.
The last data byte on the bus is always contained in the SM0DAT; thereby, ensuring that correct data is
transmitted from the master to the slave in the event of lost arbitration.
Address Register
The slave address is held in the SM0ADR Address register. When in slave mode, the 7-bit address is
held in the seven most significant bits, the least of which is bit 0. Bit 0 recognizes the general call
address (0x00) when set to logic ‘1’. When the SMBus hardware is operating in master mode, the con-
tents of the SM0ADR Address register are ignored.
Status Register
The status of the SMBus is held in the SM0STA Status register as one of 31 different 8-bit status
codes. Each 8-bit status code corresponds to a unique SMBus state. When SI = ‘1’, the three least sig-
nificant bits of the status code are set to zero and the five most significant bits vary. All possible status
codes are multiples of eight; which, in software, allows the status code to act as an index to branch to
service routines by allowing 8 bytes of code to service the state or jump to a more extensive routine.
Set the SI flag to logic ‘1’ to define the contents of the SM0STA register for software use. Software
must not write to the SM0STA because doing so yields uncertain results. Refer to Tables 6-1 through
6-4 for the 31 SMBus states and their corresponding status codes.
Table 19:Master Transmitter Mode (1 of 2)
Status
Code
(SM0STA)
SMBus1 Hardware
Status
Application Software Response
SMBus Hardware - Next
Action
To/From
SM0DAT
To SM0CON
STA STO
SI
AA
08H
START condition transmit-
ted
Load SLA+W
X
0
X
SLA+W transmitted; ACK bit
received
10H
Repeat START transmit-
ted
Load SLA+W
or
X
0
X
SLA+W transmitted; ACK bit
received
Load SLA+R
X
0
X
SLA+W transmitted;
SMBus switched to MST/REC
mode
18H
SLA+W transmitted;
ACK received
Load data
byte or
0
X
Data byte transmitted; ACK
received
No SM0DAT
action
1
0
X
Repeat START transmitted
0
1
0
X
STOP condition transmitted
STO flag reset
1
0
X
STOP condition followed by
START condition transmitted;
STO flag reset
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