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参数资料
| 型号： | SSTUB32S868DHLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | IC REGIST BUFF 25BIT DDR2 176BGA |
| 产品变化通告： | Product Discontinuation 09/Dec/2011 |
| 标准包装： | 1,000 |
| 逻辑类型： | DDR2 的寄存缓冲器 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 位数： | 25 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 176-TFBGA |
| 供应商设备封装： | 176-CABGA（6x15） |
| 包装： | 带卷 (TR) |
16
ICSSSTUB32S868D
Advance Information
08/14/06
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN
MAX
Units
fmax
Max input clock frequency
410
MHz
tPDM
Propagation delay, single
bit switching
CK
↑ to CK#↓ Qn
1.2
1.9
ns
tLH
Low to High propagation
delay
CK
↑ to CK#↓ to QERR#
1.2
3
ns
tHL
High to low propagation
delay
CK
↑ to CK#↓ to QERR#
1
2.4
ns
tPDMSS
Propagation delay
simultaneous switching
CK
↑ to CK#↓ Qn
2
ns
tPHL
High to low propagation
delay
Reset#
↓ to Qn↓
3ns
tPLH
Low to High propagation
delay
Reset#
↓ to QERR#↑
3ns
1. Guaranteed by design, not 100% tested in production.
(over recommended operating free-air temperature range, unless otherwise noted)
Timing Requirements
NOTE 1
This parameter is not necessarily production tested.
NOTE 2
VREF must be held at a valid input voltage level and data inputs must be held low for a minimum time of
tACT (max) after RESET# is taken high.
NOTE 3
VREF, Data and clock inputs must be held at valid voltage levels (not floating) a minimum time of tINACT
(max) after RESET# is taken low.
Symbol
Parameter
Min
Max
Unit
fclock
Clock frequency
-
410
MHz
tW
Pulse duration, CK, CK# HIGH or LOW
1-
ns
tACT
Differential inputs active time (See Notes 1 and 2)
-10
ns
tINACT Differential inputs inactive time (See Notes 1 and 3)
-15
ns
tSU
Setup time
DCS before CK , CK# , CSR# high;
CSR# before CK , CK# , DCS# high
0.7
-
ns
Setup time
DCS# before CK , CK# , CSR# low
0.5
-
ns
Setup time
DODT, DCKE and data before CK , CK
#
0.5
-
ns
Setup time
PAR_IN before CK , CK#
0.5
-
ns
tH
Hold time
DCS#, DODT, DCKE and data after CK , CK
#
0.
6
-
ns
Hold time
PAR_IN after CK , CK#
0.5
-
ns
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