参数资料
型号: ST16C1551
厂商: Exar Corporation
英文描述: UART with 16-Byte FIFO(通用异步接收器/发送器(带16字节的先进先出))
中文描述: 的UART具有16字节FIFO(通用异步接收器/发送器(带16字节的先进先出))
文件页数: 12/32页
文件大小: 418K
代理商: ST16C1551
ST16C1550/51
12
Rev. 3.10
FIFO monitoring. IER bit-5 additionally enables/dis-
ables the DMA monitor signals TXRDY and RXRDY in
the ISR register (bits 4-5). These signals monitor the
FIFO fill levels when the FIFOs are enabled for block
mode operations (DMA). Soft resets are useful when
the user desires the capability of resetting an exter-
nally connected device only. During special mode
operation, soft resets from MCR bit 2 are ORd with
resets on the input pin, RESET. Therefore both reset
types will be seen at the RST pin.
Loopback Mode
The internal loopback capability allows onboard diag-
nostics. In the loopback mode the normal modem
interface pins are disconnected and reconfigured for
loopback internally. MCR register bits 0-3 are used for
controlling loopback diagnostic testing. In the
loopback mode INT enable and MCR bit-2 in the MCR
register (bits 3/2) control the modem -RI and -CD
inputs respectively. MCR signals -DTR and -RTS (bits
0-1) are used to control the modem -CTS and -DSR
inputs respectively. The transmitter output (TX) and
the receiver input (RX) are disconnected from their
associated interface pins, and instead are connected
together internally (See Figure 4). The -CTS, -DSR, -
CD, and -RI are disconnected from their normal
modem control inputs pins, and instead are connected
internally to -DTR, -RTS, INT enable and MCR bit-2.
Loopback test data is entered into the transmit holding
register via the user data bus interface, D0-D7. The
transmit UART serializes the data and passes the
serial data to the receive UART via the internal
loopback connection. The receive UART converts the
serial data back into parallel data that is then made
available at the user data interface, D0-D7. The user
optionally compares the received data to the initial
transmitted data for verifying error free operation of
the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts
are fully operational. The Modem Control Interrupts
are also operational. However, the interrupts can only
be read using lower four bits of the Modem Control
Register (MCR bits 0-3) instead of the four Modem
Status Register bits 4-7. The interrupts are still con-
trolled by the IER.
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