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参数资料
| 型号： | ST16C1551 |
| 厂商： | Exar Corporation |
| 英文描述： | UART with 16-Byte FIFO(通用异步接收器/发送器（带16字节的先进先出）) |
| 中文描述： | 的UART具有16字节FIFO（通用异步接收器/发送器（带16字节的先进先出）） |
| 文件页数： | 9/32页 |
| 文件大小： | 418K |
| 代理商： | ST16C1551 |
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ST16C1550/51
9
Rev. 3.10
Table 3, INTERNAL REGISTER DECODE
A2
A1
A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1*
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Holding Register
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
Scratchpad Register
Baud Rate Register Set (DLL/DLM): Note *2
0
0
0
0
0
1
LSB of Divisor Latch
MSB of Divisor Latch
LSB of Divisor Latch
MSB of Divisor Latch
Note 1* The General Register set is accessible only when CS is a logic 0.
Note 2* The Baud Rate register set is accessible only when CS is a logic 0 and LCR bit-7 is a logic 1.
FIFO Operation
The 16 byte transmit and receive data FIFOs are
enabled by the FIFO Control Register (FCR) bit-0. The
user can set the receive trigger level via FCR bits 6/
7 and the transmit trigger level via FCR bits 4/5. The
transmit interrupt trigger level is set to 16 following a
reset. The receiver FIFO section includes a time-out
function to ensure data is delivered to the external
CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following
the loading of a character or the receive trigger level
has not been reached.
Time-out Interrupts
The interrupts are enabled by IER bits 0-3. Care must
be taken when handling these interrupts. Following a
reset the transmitter interrupt is enabled, the 155X will
issue an interrupt to indicate that transmit holding
register is empty. This interrupt must be serviced prior
to continuing operations. The LSR register provides
the current singular highest priority interrupt only. A
condition can exist where a higher priority interrupt
may mask the lower priority interrupt(s). Only after
servicing the higher pending interrupt will the lower
priority interrupt(s) be reflected in the status register.
Servicing the interrupt without investigating further
interrupt conditions can result in data errors.
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-3).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger
level. In this case the 155X FIFO may hold more
characters than the programmed trigger level. Follow-
ing the removal of a data byte, the user should recheck
LSR bit-0 for additional characters. A Receive Time
Out will not occur if the receive FIFO is empty. The
time out counter is reset at the center of each stop bit
received or each time the receive holding register
(RHR) is read.. The actual time out value is T (
T
ime
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| ST16C2550CP40 | Power Supply IC; Supply Voltage Max:6V; Output Voltage:1.3V; Package/Case:20-TSSOP; Leaded Process Compatible:No; Output Voltage Max:1.3V; Peak Reflow Compatible (260 C):No; Supply Voltage Min:2.7V; Mounting Type:Surface Mount |
相关代理商/技术参数 |
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| ST16C1551CJ28 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551CJ28-F | 功能描述:UART 接口集成电路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C1551CP28 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551CQ48 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551CQ48-F | 功能描述:UART 接口集成电路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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