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参数资料
| 型号： | ST16C1551 |
| 厂商： | Exar Corporation |
| 英文描述： | UART with 16-Byte FIFO(通用异步接收器/发送器（带16字节的先进先出）) |
| 中文描述： | 的UART具有16字节FIFO（通用异步接收器/发送器（带16字节的先进先出）） |
| 文件页数： | 17/32页 |
| 文件大小： | 418K |
| 代理商： | ST16C1551 |
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ST16C1550/51
17
Rev. 3.10
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a 1 when other FCR bits are written to or
they will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-3:
Logic 0 = Set DMA mode 0. (normal default condi-
tion)
Logic 1 = Set DMA mode 1.
Transmit operation in mode 0:
When the 155X is in the ST16C450 mode (FIFOs
disabled, FCR bit-0 = logic 0) or in the FIFO mode
(FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic
0) and when there are no characters in the transmit
FIFO or transmit holding register, TXRDY, bit 4 in the
ISR will be a logic 0. Once active TXRDY will go to a
logic 1 after the first character is loaded into the
transmit holding register.
Receive operation in mode 0:
When the 155X is in mode 0 (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and there is at least one character in the
receive FIFO, RXRDY, bit 5 in the ISR will be a logic
0. Once active, RXRDY will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode 1:
When the 155X is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), TXRDY bit-4 in the ISR register
will be a logic 1 when the transmit FIFO is completely
full. TXRDY will be a logic 0 if one or more FIFO
locations are empty.
Receive operation in mode 1:
When the 155X is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred,
RXRDY, bit-5 in the ISR will go to a logic 0. Once
activated, RXRDY will go to a logic 1 after there are no
more characters in the FIFO.
FCR BIT 4-5: (logic 0 or cleared is the default condi-
tion, TX trigger level = 1)
These bits are used to set the trigger level for the
transmit FIFO interrupt. The 155X will issue a transmit
empty interrupt when the number of characters in
FIFO drops below the selected trigger level.
BIT-5
BIT-4
TX FIFO trigger level
0
0
1
1
0
1
0
1
01
04
08
14
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level = 1)
These bits are used to set the trigger level for the
receive FIFO interrupt.
An interrupt is generated when the number of charac-
ters in the FIFO equals the programmed trigger level.
However the FIFO will continue to be loaded until it is
full.
BIT-7
BIT-6
RX FIFO trigger level
0
0
1
1
0
1
0
1
01
04
08
14
Interrupt Status Register (ISR)
The 155X provides four levels of prioritized interrupts
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| ST16C1551CJ28 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551CJ28-F | 功能描述:UART 接口集成电路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C1551CP28 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551CQ48 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551CQ48-F | 功能描述:UART 接口集成电路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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