参数资料
型号: ST16C2550
厂商: Exar Corporation
英文描述: Dual UART with 16-Byte of Transmit and Receive FIFO(双通用异步接收器/发送器(带16字节接收和发送先进先出))
中文描述: 双UART具有16的发送和接收FIFO(双通用异步接收器/发送器(带16字节接收和发送先进先出字节))
文件页数: 18/34页
文件大小: 314K
代理商: ST16C2550
ST16C2550
18
Rev. 3.40
Table 6, INTERRUPT SOURCE TABLE
Priority
Level
[ ISR BITS ]
Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
2
2
3
4
X
0
0
1
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
None
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared s the default condition)
These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (See Interrupt Source
Table).
ISR BIT 4-5: (logic 0 or cleared s the default condition)
Not Used - initialized to a logic 0.
ISR BIT 6-7: (logic 0 or cleared s the default condition)
These bits are set to a logic 0 when the FIFO’s are not
being used in the 16C450 mode. They are set to a logic
1 when the FIFO’s are enabled in the ST16C2550 mode.
Line Control Register (LCR)
The Line Control Register is used to specify the asyn-
chronous data communication format. The word length,
the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared s he default condition)
These two bits specify the word length to be transmitted
or received.
BIT-1
BIT-0
Word length
0
0
1
1
0
1
0
1
5
6
7
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
Word length
Stop bit
length
(Bit time(s))
0
1
1
5,6,7,8
5
6,7,8
1
1-1/2
2
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity. (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
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